Add support for DisplayPort driver on SnapDragon

From: Chandan Uddaraju <[email protected]>

drivers/gpu/drm/msm/dp/dp_parser.c new file +5 -0

+				clk->type = DSS_CLK_PCLK;
+			else
+				clk->type = DSS_CLK_AHB;
+		}
+	}

Hello,

Quoted 1 line · Tanmay Shah

From: Chandan Uddaraju <[email protected]>

[skipped]

drivers/gpu/drm/msm/dp/dp_parser.c line 213

Quoted 12 lines

drivers/gpu/drm/msm/dp/dp_parser.c new file +12 -0

+		} else if ((dp_parser_check_prefix("ctrl", clk_name) ||
+			   dp_parser_check_prefix("stream", clk_name))  &&
+			   ctrl_clk_index < ctrl_clk_count) {
+			struct dss_clk *clk =
+				&ctrl_power->clk_config[ctrl_clk_index];
+			strlcpy(clk->clk_name, clk_name, sizeof(clk->clk_name));
+			ctrl_clk_index++;
+
+			if (!strncmp(clk_name, "ctrl_link",
+					strlen("ctrl_link")) ||
+					!strncmp(clk_name, "stream_pixel",
+					strlen("ctrl_pixel")))

This should be "stream_pixel", I believe. I don't like macros, but most probably it would help here. Also function/brace alignment could be better (sorry, it really hides the issue here).

Quoted 7 lines

drivers/gpu/drm/msm/dp/dp_parser.c new file +5 -0

+				clk->type = DSS_CLK_PCLK;
+			else
+				clk->type = DSS_CLK_AHB;
+		}
+	}

Quoted 7 lines · Dmitry Baryshkov

Hello,

Quoted 1 line · Tanmay Shah

From: Chandan Uddaraju <[email protected]>

[skipped]

Quoted 17 lines

drivers/gpu/drm/msm/dp/dp_parser.c line 213

Quoted 12 lines

drivers/gpu/drm/msm/dp/dp_parser.c new file +12 -0

+		} else if ((dp_parser_check_prefix("ctrl", clk_name) ||
+			   dp_parser_check_prefix("stream", clk_name))  &&
+			   ctrl_clk_index < ctrl_clk_count) {
+			struct dss_clk *clk =
+				&ctrl_power->clk_config[ctrl_clk_index];
+			strlcpy(clk->clk_name, clk_name, sizeof(clk->clk_name));
+			ctrl_clk_index++;
+
+			if (!strncmp(clk_name, "ctrl_link",
+					strlen("ctrl_link")) ||
+					!strncmp(clk_name, "stream_pixel",
+					strlen("ctrl_pixel")))

This should be "stream_pixel", I believe. I don't like macros, but most probably it would help here. Also function/brace alignment could be better (sorry, it really hides the issue here).

Thanks for reviews and good catch!! I completely missed it when I renamed "ctrl_pixel".
Use of "stream_pixel" is very limited. So, instead of macros direct name is used.
Fixing function and brace alignment sounds good idea insted.

Quoted 1 line

Quoted 6 lines

drivers/gpu/drm/msm/dp/dp_parser.c line 218

Quoted 6 lines

drivers/gpu/drm/msm/dp/dp_parser.c new file +5 -0

+				clk->type = DSS_CLK_PCLK;
+			else
+				clk->type = DSS_CLK_AHB;
+		}
+	}

_______________________________________________
dri-devel mailing list
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https://lists.freedesktop.org/mailman/listinfo/dri-devel

From: Chandan Uddaraju <[email protected]>

Add the needed DP PLL specific files to support
display port interface on msm targets.

drivers/gpu/drm/msm/dp/dp_pll_private.h new file +24 -0

new file mode 100644
index 000000000000..475ba6ed59ab
@@ -0,0 +1,98 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef __DP_PLL_10NM_H
+#define __DP_PLL_10NM_H
+
+#include "dp_pll.h"
+#include "dp_reg.h"
+
+#define DP_VCO_HSCLK_RATE_1620MHZDIV1000    1620000UL
+#define DP_VCO_HSCLK_RATE_2700MHZDIV1000    2700000UL
+#define DP_VCO_HSCLK_RATE_5400MHZDIV1000    5400000UL
+#define DP_VCO_HSCLK_RATE_8100MHZDIV1000    8100000UL
+
+#define NUM_DP_CLOCKS_MAX            6
+
+#define DP_PHY_PLL_POLL_SLEEP_US        500
+#define DP_PHY_PLL_POLL_TIMEOUT_US        10000
+
+#define DP_VCO_RATE_8100MHZDIV1000        8100000UL
+#define DP_VCO_RATE_9720MHZDIV1000        9720000UL
+#define DP_VCO_RATE_10800MHZDIV1000        10800000UL

drivers/gpu/drm/msm/dp/dp_pll_private.h new file +44 -0

+    u32 num_hws;
+
+    /* lane and orientation settings */
+    u8 lane_cnt;
+    u8 orientation;
+
+    /* COM PHY settings */
+    u32 hsclk_sel;
+    u32 dec_start_mode0;
+    u32 div_frac_start1_mode0;
+    u32 div_frac_start2_mode0;
+    u32 div_frac_start3_mode0;
+    u32 integloop_gain0_mode0;
+    u32 integloop_gain1_mode0;
+    u32 vco_tune_map;
+    u32 lock_cmp1_mode0;
+    u32 lock_cmp2_mode0;
+    u32 lock_cmp3_mode0;
+    u32 lock_cmp_en;
+
+    /* PHY vco divider */
+    u32 phy_vco_div;
+    /*
+     * Certain pll's needs to update the same vco rate after resume in
+     * suspend/resume scenario. Cached the vco rate for such plls.
+     */
+    unsigned long    vco_cached_rate;
+    u32        cached_cfg0;
+    u32        cached_cfg1;
+    u32        cached_outdiv;
+
+    uint32_t index;
+};
+
+static inline struct dp_pll_vco_clk *to_dp_vco_hw(struct clk_hw *hw)
+{
+    return container_of(hw, struct dp_pll_vco_clk, hw);
+}
+
+#define to_msm_dp_pll(vco) ((struct msm_dp_pll *)vco->priv)
+
+#define to_dp_pll_db(x)    ((struct dp_pll_db *)x->priv)
+
+int dp_vco_set_rate_10nm(struct clk_hw *hw, unsigned long rate,

Quoted 4 lines · Tanmay Shah

From: Chandan Uddaraju <[email protected]>

Add the needed DP PLL specific files to support
display port interface on msm targets.

[skipped]

Quoted 36 lines

drivers/gpu/drm/msm/dp/dp_pll_private.h new file +3 -0

new file mode 100644
index 000000000000..475ba6ed59ab
@@ -0,0 +1,98 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2016-2020, The Linux Foundation. All rights 

reserved.
+ */

drivers/gpu/drm/msm/dp/dp_pll_private.h new file +25 -0

+
+#ifndef __DP_PLL_10NM_H
+#define __DP_PLL_10NM_H
+
+#include "dp_pll.h"
+#include "dp_reg.h"
+
+#define DP_VCO_HSCLK_RATE_1620MHZDIV1000    1620000UL
+#define DP_VCO_HSCLK_RATE_2700MHZDIV1000    2700000UL
+#define DP_VCO_HSCLK_RATE_5400MHZDIV1000    5400000UL
+#define DP_VCO_HSCLK_RATE_8100MHZDIV1000    8100000UL
+
+#define NUM_DP_CLOCKS_MAX            6
+
+#define DP_PHY_PLL_POLL_SLEEP_US        500
+#define DP_PHY_PLL_POLL_TIMEOUT_US        10000
+
+#define DP_VCO_RATE_8100MHZDIV1000        8100000UL
+#define DP_VCO_RATE_9720MHZDIV1000        9720000UL
+#define DP_VCO_RATE_10800MHZDIV1000        10800000UL
+
+struct dp_pll_vco_clk {
+    struct clk_hw hw;
+    unsigned long    rate;        /* current vco rate */
+    u64        min_rate;    /* min vco rate */

drivers/gpu/drm/msm/dp/dp_pll_private.h line 34

Quoted 5 lines

drivers/gpu/drm/msm/dp/dp_pll_private.h new file +5 -0

+    u64        max_rate;    /* max vco rate */
+    void        *priv;
+};
+
+struct dp_pll_db {

This struct should probably go into dp_pll_10nm.c. dp_pll_7nm.c, for example, will use slightly different structure.

drivers/gpu/drm/msm/dp/dp_pll_private.h line 42

Quoted 8 lines

drivers/gpu/drm/msm/dp/dp_pll_private.h new file +8 -0

+    struct msm_dp_pll *base;
+
+    int id;
+    struct platform_device *pdev;
+
+    /* private clocks: */
+    bool fixed_factor_clk[NUM_DP_CLOCKS_MAX];
+    struct clk_hw *hws[NUM_DP_CLOCKS_MAX];

Then these two fields can use exact number of clocks rather than NUM_DP_CLOCKS_MAX.

Quoted 50 lines

drivers/gpu/drm/msm/dp/dp_pll_private.h new file +24 -0

+    u32 num_hws;
+
+    /* lane and orientation settings */
+    u8 lane_cnt;
+    u8 orientation;
+
+    /* COM PHY settings */
+    u32 hsclk_sel;
+    u32 dec_start_mode0;
+    u32 div_frac_start1_mode0;
+    u32 div_frac_start2_mode0;
+    u32 div_frac_start3_mode0;
+    u32 integloop_gain0_mode0;
+    u32 integloop_gain1_mode0;
+    u32 vco_tune_map;
+    u32 lock_cmp1_mode0;
+    u32 lock_cmp2_mode0;
+    u32 lock_cmp3_mode0;
+    u32 lock_cmp_en;
+
+    /* PHY vco divider */
+    u32 phy_vco_div;
+    /*
+     * Certain pll's needs to update the same vco rate after resume 

in

drivers/gpu/drm/msm/dp/dp_pll_private.h new file +25 -0

+     * suspend/resume scenario. Cached the vco rate for such plls.
+     */
+    unsigned long    vco_cached_rate;
+    u32        cached_cfg0;
+    u32        cached_cfg1;
+    u32        cached_outdiv;
+
+    uint32_t index;
+};
+
+static inline struct dp_pll_vco_clk *to_dp_vco_hw(struct clk_hw *hw)
+{
+    return container_of(hw, struct dp_pll_vco_clk, hw);
+}
+
+#define to_msm_dp_pll(vco) ((struct msm_dp_pll *)vco->priv)
+
+#define to_dp_pll_db(x)    ((struct dp_pll_db *)x->priv)
+
+int dp_vco_set_rate_10nm(struct clk_hw *hw, unsigned long rate,
+                unsigned long parent_rate);
+unsigned long dp_vco_recalc_rate_10nm(struct clk_hw *hw,
+                unsigned long parent_rate);
+long dp_vco_round_rate_10nm(struct clk_hw *hw, unsigned long rate,
+                unsigned long *parent_rate);

drivers/gpu/drm/msm/dp/dp_pll_private.h line 96

Quoted 5 lines

drivers/gpu/drm/msm/dp/dp_pll_private.h new file +5 -0

+int dp_vco_prepare_10nm(struct clk_hw *hw);
+void dp_vco_unprepare_10nm(struct clk_hw *hw);
+
+int msm_dp_pll_10nm_init(struct msm_dp_pll *dp_pll, int id);
+void msm_dp_pll_10nm_deinit(struct msm_dp_pll *dp_pll);

These functions don't seem to be used outside of dp_pll_10nm. What about making them static?

Quoted 43 lines · Dmitry Baryshkov

Quoted 4 lines · Tanmay Shah

From: Chandan Uddaraju <[email protected]>

Add the needed DP PLL specific files to support
display port interface on msm targets.

[skipped]

Quoted 35 lines

drivers/gpu/drm/msm/dp/dp_pll_private.h new file +29 -0

new file mode 100644
index 000000000000..475ba6ed59ab
@@ -0,0 +1,98 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef __DP_PLL_10NM_H
+#define __DP_PLL_10NM_H
+
+#include "dp_pll.h"
+#include "dp_reg.h"
+
+#define DP_VCO_HSCLK_RATE_1620MHZDIV1000    1620000UL
+#define DP_VCO_HSCLK_RATE_2700MHZDIV1000    2700000UL
+#define DP_VCO_HSCLK_RATE_5400MHZDIV1000    5400000UL
+#define DP_VCO_HSCLK_RATE_8100MHZDIV1000    8100000UL
+
+#define NUM_DP_CLOCKS_MAX            6
+
+#define DP_PHY_PLL_POLL_SLEEP_US        500
+#define DP_PHY_PLL_POLL_TIMEOUT_US        10000
+
+#define DP_VCO_RATE_8100MHZDIV1000        8100000UL
+#define DP_VCO_RATE_9720MHZDIV1000        9720000UL
+#define DP_VCO_RATE_10800MHZDIV1000        10800000UL
+
+struct dp_pll_vco_clk {
+    struct clk_hw hw;
+    unsigned long    rate;        /* current vco rate */
+    u64        min_rate;    /* min vco rate */

Quoted 9 lines

drivers/gpu/drm/msm/dp/dp_pll_private.h line 34

Quoted 5 lines

drivers/gpu/drm/msm/dp/dp_pll_private.h new file +5 -0

+    u64        max_rate;    /* max vco rate */
+    void        *priv;
+};
+
+struct dp_pll_db {

This struct should probably go into dp_pll_10nm.c. dp_pll_7nm.c, for example, will use slightly different structure.

Sure, it sounds good. I will give it try. Thanks!

Quoted 12 lines

drivers/gpu/drm/msm/dp/dp_pll_private.h line 42

Quoted 8 lines

drivers/gpu/drm/msm/dp/dp_pll_private.h new file +8 -0

+    struct msm_dp_pll *base;
+
+    int id;
+    struct platform_device *pdev;
+
+    /* private clocks: */
+    bool fixed_factor_clk[NUM_DP_CLOCKS_MAX];
+    struct clk_hw *hws[NUM_DP_CLOCKS_MAX];

Then these two fields can use exact number of clocks rather than NUM_DP_CLOCKS_MAX.

I didn't get this. I think NUM_DP_CLOCKS_MAX is doing same?

Quoted 49 lines

Quoted 49 lines

drivers/gpu/drm/msm/dp/dp_pll_private.h new file +49 -0

+    u32 num_hws;
+
+    /* lane and orientation settings */
+    u8 lane_cnt;
+    u8 orientation;
+
+    /* COM PHY settings */
+    u32 hsclk_sel;
+    u32 dec_start_mode0;
+    u32 div_frac_start1_mode0;
+    u32 div_frac_start2_mode0;
+    u32 div_frac_start3_mode0;
+    u32 integloop_gain0_mode0;
+    u32 integloop_gain1_mode0;
+    u32 vco_tune_map;
+    u32 lock_cmp1_mode0;
+    u32 lock_cmp2_mode0;
+    u32 lock_cmp3_mode0;
+    u32 lock_cmp_en;
+
+    /* PHY vco divider */
+    u32 phy_vco_div;
+    /*
+     * Certain pll's needs to update the same vco rate after resume in
+     * suspend/resume scenario. Cached the vco rate for such plls.
+     */
+    unsigned long    vco_cached_rate;
+    u32        cached_cfg0;
+    u32        cached_cfg1;
+    u32        cached_outdiv;
+
+    uint32_t index;
+};
+
+static inline struct dp_pll_vco_clk *to_dp_vco_hw(struct clk_hw *hw)
+{
+    return container_of(hw, struct dp_pll_vco_clk, hw);
+}
+
+#define to_msm_dp_pll(vco) ((struct msm_dp_pll *)vco->priv)
+
+#define to_dp_pll_db(x)    ((struct dp_pll_db *)x->priv)
+
+int dp_vco_set_rate_10nm(struct clk_hw *hw, unsigned long rate,
+                unsigned long parent_rate);
+unsigned long dp_vco_recalc_rate_10nm(struct clk_hw *hw,
+                unsigned long parent_rate);
+long dp_vco_round_rate_10nm(struct clk_hw *hw, unsigned long rate,
+                unsigned long *parent_rate);

Quoted 8 lines

drivers/gpu/drm/msm/dp/dp_pll_private.h line 96

Quoted 5 lines

drivers/gpu/drm/msm/dp/dp_pll_private.h new file +5 -0

+int dp_vco_prepare_10nm(struct clk_hw *hw);
+void dp_vco_unprepare_10nm(struct clk_hw *hw);
+
+int msm_dp_pll_10nm_init(struct msm_dp_pll *dp_pll, int id);
+void msm_dp_pll_10nm_deinit(struct msm_dp_pll *dp_pll);

These functions don't seem to be used outside of dp_pll_10nm. What about making them static?

I can't declare static to "init" and "deinit" as they are exported to dp_pll.c. Rest of them I can move to dp_pll_10nm and then define static.

Quoted 70 lines · Tanmay Shah

Quoted 44 lines · Dmitry Baryshkov

Quoted 4 lines · Tanmay Shah

From: Chandan Uddaraju <[email protected]>

Add the needed DP PLL specific files to support
display port interface on msm targets.

[skipped]

Quoted 36 lines

drivers/gpu/drm/msm/dp/dp_pll_private.h new file +3 -0

new file mode 100644
index 000000000000..475ba6ed59ab
@@ -0,0 +1,98 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2016-2020, The Linux Foundation. All rights 

reserved.
+ */

drivers/gpu/drm/msm/dp/dp_pll_private.h new file +25 -0

+
+#ifndef __DP_PLL_10NM_H
+#define __DP_PLL_10NM_H
+
+#include "dp_pll.h"
+#include "dp_reg.h"
+
+#define DP_VCO_HSCLK_RATE_1620MHZDIV1000    1620000UL
+#define DP_VCO_HSCLK_RATE_2700MHZDIV1000    2700000UL
+#define DP_VCO_HSCLK_RATE_5400MHZDIV1000    5400000UL
+#define DP_VCO_HSCLK_RATE_8100MHZDIV1000    8100000UL
+
+#define NUM_DP_CLOCKS_MAX            6
+
+#define DP_PHY_PLL_POLL_SLEEP_US        500
+#define DP_PHY_PLL_POLL_TIMEOUT_US        10000
+
+#define DP_VCO_RATE_8100MHZDIV1000        8100000UL
+#define DP_VCO_RATE_9720MHZDIV1000        9720000UL
+#define DP_VCO_RATE_10800MHZDIV1000        10800000UL
+
+struct dp_pll_vco_clk {
+    struct clk_hw hw;
+    unsigned long    rate;        /* current vco rate */
+    u64        min_rate;    /* min vco rate */

Quoted 9 lines

drivers/gpu/drm/msm/dp/dp_pll_private.h line 34

Quoted 5 lines

drivers/gpu/drm/msm/dp/dp_pll_private.h new file +5 -0

+    u64        max_rate;    /* max vco rate */
+    void        *priv;
+};
+
+struct dp_pll_db {

This struct should probably go into dp_pll_10nm.c. dp_pll_7nm.c, for example, will use slightly different structure.

Sure, it sounds good. I will give it try. Thanks!

Quoted 12 lines

drivers/gpu/drm/msm/dp/dp_pll_private.h line 42

Quoted 8 lines

drivers/gpu/drm/msm/dp/dp_pll_private.h new file +8 -0

+    struct msm_dp_pll *base;
+
+    int id;
+    struct platform_device *pdev;
+
+    /* private clocks: */
+    bool fixed_factor_clk[NUM_DP_CLOCKS_MAX];
+    struct clk_hw *hws[NUM_DP_CLOCKS_MAX];

Then these two fields can use exact number of clocks rather than NUM_DP_CLOCKS_MAX.

Quoted 1 line

I didn't get this. I think NUM_DP_CLOCKS_MAX is doing same?

Not exactly. We'd need fixed_factor_clk[4] for 10nm rather than 6. It's not that important, just a small nitpick.

Quoted 60 lines

Quoted 59 lines

Quoted 46 lines

drivers/gpu/drm/msm/dp/dp_pll_private.h new file +24 -0

+    u32 num_hws;
+
+    /* lane and orientation settings */
+    u8 lane_cnt;
+    u8 orientation;
+
+    /* COM PHY settings */
+    u32 hsclk_sel;
+    u32 dec_start_mode0;
+    u32 div_frac_start1_mode0;
+    u32 div_frac_start2_mode0;
+    u32 div_frac_start3_mode0;
+    u32 integloop_gain0_mode0;
+    u32 integloop_gain1_mode0;
+    u32 vco_tune_map;
+    u32 lock_cmp1_mode0;
+    u32 lock_cmp2_mode0;
+    u32 lock_cmp3_mode0;
+    u32 lock_cmp_en;
+
+    /* PHY vco divider */
+    u32 phy_vco_div;
+    /*
+     * Certain pll's needs to update the same vco rate after resume 

in

drivers/gpu/drm/msm/dp/dp_pll_private.h new file +11 -0

+     * suspend/resume scenario. Cached the vco rate for such plls.
+     */
+    unsigned long    vco_cached_rate;
+    u32        cached_cfg0;
+    u32        cached_cfg1;
+    u32        cached_outdiv;
+
+    uint32_t index;
+};
+
+static inline struct dp_pll_vco_clk *to_dp_vco_hw(struct clk_hw 

*hw)

drivers/gpu/drm/msm/dp/dp_pll_private.h new file +9 -0

+{
+    return container_of(hw, struct dp_pll_vco_clk, hw);
+}
+
+#define to_msm_dp_pll(vco) ((struct msm_dp_pll *)vco->priv)
+
+#define to_dp_pll_db(x)    ((struct dp_pll_db *)x->priv)
+
+int dp_vco_set_rate_10nm(struct clk_hw *hw, unsigned long rate,

drivers/gpu/drm/msm/dp/dp_pll_private.h line 96

Quoted 10 lines

drivers/gpu/drm/msm/dp/dp_pll_private.h new file +10 -0

+                unsigned long parent_rate);
+unsigned long dp_vco_recalc_rate_10nm(struct clk_hw *hw,
+                unsigned long parent_rate);
+long dp_vco_round_rate_10nm(struct clk_hw *hw, unsigned long rate,
+                unsigned long *parent_rate);
+int dp_vco_prepare_10nm(struct clk_hw *hw);
+void dp_vco_unprepare_10nm(struct clk_hw *hw);
+
+int msm_dp_pll_10nm_init(struct msm_dp_pll *dp_pll, int id);
+void msm_dp_pll_10nm_deinit(struct msm_dp_pll *dp_pll);

These functions don't seem to be used outside of dp_pll_10nm. What about making them static?

Quoted 2 lines

I can't declare static to "init" and "deinit" as they are exported to dp_pll.c. Rest of them I can move to dp_pll_10nm and then define static.

Please exuse me for not being exact enough. Of course I meant dp_vco_FOO_10nm() functions, not init/exit.

BTW: as I'm looking onto 7nm dp pll, which naming would you prefer?

We can have separate DP_PLL_10nm/DP_PLL_7nm namespaces (as DSI PLLs do) or I can override only a set of constants (like downstream driver does).

Quoted 4 lines · Tanmay Shah

From: Chandan Uddaraju <[email protected]>

Add the needed DP PLL specific files to support
display port interface on msm targets.

[skipped]

Review

Quoted 1 line

(quoted diff) +0 -0

b/drivers/gpu/drm/msm/dp/dp_pll_private.h

Quoted 34 lines

new file mode 100644
index 000000000000..475ba6ed59ab

drivers/gpu/drm/msm/dp/dp_pll_private.h new file +29 -0

@@ -0,0 +1,98 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef __DP_PLL_10NM_H
+#define __DP_PLL_10NM_H
+
+#include "dp_pll.h"
+#include "dp_reg.h"
+
+#define DP_VCO_HSCLK_RATE_1620MHZDIV1000    1620000UL
+#define DP_VCO_HSCLK_RATE_2700MHZDIV1000    2700000UL
+#define DP_VCO_HSCLK_RATE_5400MHZDIV1000    5400000UL
+#define DP_VCO_HSCLK_RATE_8100MHZDIV1000    8100000UL
+
+#define NUM_DP_CLOCKS_MAX            6
+
+#define DP_PHY_PLL_POLL_SLEEP_US        500
+#define DP_PHY_PLL_POLL_TIMEOUT_US        10000
+
+#define DP_VCO_RATE_8100MHZDIV1000        8100000UL
+#define DP_VCO_RATE_9720MHZDIV1000        9720000UL
+#define DP_VCO_RATE_10800MHZDIV1000        10800000UL
+
+struct dp_pll_vco_clk {
+    struct clk_hw hw;
+    unsigned long    rate;        /* current vco rate */
+    u64        min_rate;    /* min vco rate */

drivers/gpu/drm/msm/dp/dp_pll_private.h line 34

Quoted 5 lines

drivers/gpu/drm/msm/dp/dp_pll_private.h new file +5 -0

+    u64        max_rate;    /* max vco rate */
+    void        *priv;
+};
+
+struct dp_pll_db {

This struct should probably go into dp_pll_10nm.c. dp_pll_7nm.c, for example, will use slightly different structure.

Quoted 46 lines · Dmitry Baryshkov

Quoted 4 lines · Tanmay Shah

From: Chandan Uddaraju <[email protected]>

Add the needed DP PLL specific files to support
display port interface on msm targets.

[skipped]

Review

Quoted 1 line

(quoted diff) +0 -0

b/drivers/gpu/drm/msm/dp/dp_pll_private.h

Quoted 34 lines

new file mode 100644
index 000000000000..475ba6ed59ab

drivers/gpu/drm/msm/dp/dp_pll_private.h new file +29 -0

@@ -0,0 +1,98 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef __DP_PLL_10NM_H
+#define __DP_PLL_10NM_H
+
+#include "dp_pll.h"
+#include "dp_reg.h"
+
+#define DP_VCO_HSCLK_RATE_1620MHZDIV1000    1620000UL
+#define DP_VCO_HSCLK_RATE_2700MHZDIV1000    2700000UL
+#define DP_VCO_HSCLK_RATE_5400MHZDIV1000    5400000UL
+#define DP_VCO_HSCLK_RATE_8100MHZDIV1000    8100000UL
+
+#define NUM_DP_CLOCKS_MAX            6
+
+#define DP_PHY_PLL_POLL_SLEEP_US        500
+#define DP_PHY_PLL_POLL_TIMEOUT_US        10000
+
+#define DP_VCO_RATE_8100MHZDIV1000        8100000UL
+#define DP_VCO_RATE_9720MHZDIV1000        9720000UL
+#define DP_VCO_RATE_10800MHZDIV1000        10800000UL
+
+struct dp_pll_vco_clk {
+    struct clk_hw hw;
+    unsigned long    rate;        /* current vco rate */
+    u64        min_rate;    /* min vco rate */

Quoted 8 lines

drivers/gpu/drm/msm/dp/dp_pll_private.h line 34

Quoted 5 lines

drivers/gpu/drm/msm/dp/dp_pll_private.h new file +5 -0

+    u64        max_rate;    /* max vco rate */
+    void        *priv;
+};
+
+struct dp_pll_db {

This struct should probably go into dp_pll_10nm.c. dp_pll_7nm.c, for example, will use slightly different structure.

Note that sboyd has a WIP series to move all of the pll code out to a phy driver. If there is work already happening on 7nm support, it might be better to go with the separate phy driver approach? I'm still a bit undecided about whether to land the dp code initially with the pll stuff in drm, and then continue refactoring to move to separate phy driver upstream, or to strip out the pll code from the beginning. If you/someone is working on 7nm support, then feedback about which approach is easier is welcome.

https://lore.kernel.org/dri-devel/[email protected]/

BR,
-R
_______________________________________________
Freedreno mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/freedreno

Quoted 66 lines · Rob Clark

Quoted 46 lines · Dmitry Baryshkov

Quoted 4 lines · Tanmay Shah

From: Chandan Uddaraju <[email protected]>

Add the needed DP PLL specific files to support
display port interface on msm targets.

[skipped]

Review

Quoted 1 line

(quoted diff) +0 -0

b/drivers/gpu/drm/msm/dp/dp_pll_private.h

Quoted 34 lines

new file mode 100644
index 000000000000..475ba6ed59ab

drivers/gpu/drm/msm/dp/dp_pll_private.h new file +29 -0

@@ -0,0 +1,98 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef __DP_PLL_10NM_H
+#define __DP_PLL_10NM_H
+
+#include "dp_pll.h"
+#include "dp_reg.h"
+
+#define DP_VCO_HSCLK_RATE_1620MHZDIV1000    1620000UL
+#define DP_VCO_HSCLK_RATE_2700MHZDIV1000    2700000UL
+#define DP_VCO_HSCLK_RATE_5400MHZDIV1000    5400000UL
+#define DP_VCO_HSCLK_RATE_8100MHZDIV1000    8100000UL
+
+#define NUM_DP_CLOCKS_MAX            6
+
+#define DP_PHY_PLL_POLL_SLEEP_US        500
+#define DP_PHY_PLL_POLL_TIMEOUT_US        10000
+
+#define DP_VCO_RATE_8100MHZDIV1000        8100000UL
+#define DP_VCO_RATE_9720MHZDIV1000        9720000UL
+#define DP_VCO_RATE_10800MHZDIV1000        10800000UL
+
+struct dp_pll_vco_clk {
+    struct clk_hw hw;
+    unsigned long    rate;        /* current vco rate */
+    u64        min_rate;    /* min vco rate */

Quoted 8 lines

drivers/gpu/drm/msm/dp/dp_pll_private.h line 34

Quoted 5 lines

drivers/gpu/drm/msm/dp/dp_pll_private.h new file +5 -0

+    u64        max_rate;    /* max vco rate */
+    void        *priv;
+};
+
+struct dp_pll_db {

This struct should probably go into dp_pll_10nm.c. dp_pll_7nm.c, for example, will use slightly different structure.

Note that sboyd has a WIP series to move all of the pll code out to a phy driver. If there is work already happening on 7nm support, it might be better to go with the separate phy driver approach? I'm still a bit undecided about whether to land the dp code initially with the pll stuff in drm, and then continue refactoring to move to separate phy driver upstream, or to strip out the pll code from the beginning. If you/someone is working on 7nm support, then feedback about which approach is easier is welcome.

Quoted 2 lines

https://lore.kernel.org/dri-devel/[email protected]/

I have a sm8150/sm8250 (7nm) upstream kernel stack with DP enabled, and I have done something similar, with the PLL driver in the QMP phy, although not based on sboyd's series (along with some typec changes to negotiate the DP alt mode and get HPD events, etc.). I don't think having PLL in drm/msm makes sense, the drm/msm DP driver shouldn't need to be aware of the DP PLL/PHY driver, it only needs to set the link/pixel clock rates which are in dispcc (and those then have the PLL clocks as a parent).

FYI, since it sounds you are considering landing this: it is completely broken, for example:
- ioremap()'s to #define'd addresses in the PLL driver
- main DP driver reading/writing to registers in the PHY region, but getting the base address from devicetree was removed since earlier revisions, so it just fails completely. Look at usb3_dp_com (for example), which in dp_catalog_ctrl_usb_reset() would be used to overwrite registers already being driven by the qmp phy driver - but now the usb3_dp_com.base is never initialized.

-Jonathan

Quoted 7 lines

BR,
-R
_______________________________________________
Freedreno mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/freedreno

Quoted 14 lines · Jonathan Marek

Quoted 12 lines · Rob Clark

Quoted 10 lines · Dmitry Baryshkov

Quoted 4 lines · Tanmay Shah

From: Chandan Uddaraju <[email protected]>

Add the needed DP PLL specific files to support
display port interface on msm targets.

[skipped]

Quoted 10 lines

Quoted 10 lines

Quoted 10 lines

Review

Quoted 1 line

(quoted diff) +0 -0

b/drivers/gpu/drm/msm/dp/dp_pll_private.h

drivers/gpu/drm/msm/dp/dp_pll_private.h line 3

Quoted 8 lines

new file mode 100644
index 000000000000..475ba6ed59ab

drivers/gpu/drm/msm/dp/dp_pll_private.h new file +3 -0

@@ -0,0 +1,98 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2016-2020, The Linux Foundation. All rights

reserved.

Quoted 35 lines

Quoted 35 lines

Quoted 34 lines

Quoted 21 lines

drivers/gpu/drm/msm/dp/dp_pll_private.h new file +21 -0

+ */
+
+#ifndef __DP_PLL_10NM_H
+#define __DP_PLL_10NM_H
+
+#include "dp_pll.h"
+#include "dp_reg.h"
+
+#define DP_VCO_HSCLK_RATE_1620MHZDIV1000    1620000UL
+#define DP_VCO_HSCLK_RATE_2700MHZDIV1000    2700000UL
+#define DP_VCO_HSCLK_RATE_5400MHZDIV1000    5400000UL
+#define DP_VCO_HSCLK_RATE_8100MHZDIV1000    8100000UL
+
+#define NUM_DP_CLOCKS_MAX            6
+
+#define DP_PHY_PLL_POLL_SLEEP_US        500
+#define DP_PHY_PLL_POLL_TIMEOUT_US        10000
+
+#define DP_VCO_RATE_8100MHZDIV1000        8100000UL
+#define DP_VCO_RATE_9720MHZDIV1000        9720000UL
+#define DP_VCO_RATE_10800MHZDIV1000        10800000UL

drivers/gpu/drm/msm/dp/dp_pll_private.h line 34

Quoted 10 lines

drivers/gpu/drm/msm/dp/dp_pll_private.h new file +10 -0

+
+struct dp_pll_vco_clk {
+    struct clk_hw hw;
+    unsigned long    rate;        /* current vco rate */
+    u64        min_rate;    /* min vco rate */
+    u64        max_rate;    /* max vco rate */
+    void        *priv;
+};
+
+struct dp_pll_db {

This struct should probably go into dp_pll_10nm.c. dp_pll_7nm.c, for example, will use slightly different structure.

Quoted 10 lines

Quoted 10 lines

Note that sboyd has a WIP series to move all of the pll code out to a phy driver. If there is work already happening on 7nm support, it might be better to go with the separate phy driver approach? I'm still a bit undecided about whether to land the dp code initially with the pll stuff in drm, and then continue refactoring to move to separate phy driver upstream, or to strip out the pll code from the beginning. If you/someone is working on 7nm support, then feedback about which approach is easier is welcome.

https://lore.kernel.org/dri-devel/20200611091919.108018-1-swboyd@chromium.
org/

Quoted 10 lines

Quoted 1 line

I have a sm8150/sm8250 (7nm) upstream kernel stack with DP enabled, and I have done something similar, with the PLL driver in the QMP phy, although not based on sboyd's series (along with some typec changes to negotiate the DP alt mode and get HPD events, etc.). I don't think having PLL in drm/msm makes sense, the drm/msm DP driver shouldn't need to be aware of the DP PLL/PHY driver, it only needs to set the link/pixel clock rates which are in dispcc (and those then have the PLL clocks as a parent).

yeah, in the dp case, having phy split out makes a ton of sense.. it would maybe be a nice cleanup in other cases (dsi, hdmi) but the combination of usb+dp makes burying this in drm not so great..

It would be good if you could work w/ sboyd on this.. based on what I've seen on previous gens, it is probably a different phy driver for 7nm vs 10nm, but I think where we want to end up upstream is with phy split out of drm.

Quoted 9 lines

FYI, since it sounds you are considering landing this: it is completely broken, for example:
- ioremap()'s to #define'd addresses in the PLL driver
- main DP driver reading/writing to registers in the PHY region, but getting the base address from devicetree was removed since earlier revisions, so it just fails completely. Look at usb3_dp_com (for example), which in dp_catalog_ctrl_usb_reset() would be used to overwrite registers already being driven by the qmp phy driver - but now the usb3_dp_com.base is never initialized.

Yeah, the idea to land dp isn't that it is perfect (or even not broken), so much as having something upstream gives a common base for others to work against.. maybe we should make the dp parts 'depends on STAGING'?

I could keep a separate msm-next-dp branch that I rebase, to give a common point for folks working dp support for various different gens to coordinate work on.. that kinda sounds like a bunch of extra work for me, so might as well land what we have somehow and work together from there ;-)

But it does sound like you are making the case for including the patch to drop the pll stuff and use phy framework as part of what initially goes upstream.

BR,
-R

Quoted 10 lines

-Jonathan

Quoted 7 lines

BR,
-R
_______________________________________________
Freedreno mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/freedreno

_______________________________________________
dri-devel mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/dri-devel

Quoted 71 lines · Jonathan Marek

Quoted 66 lines · Rob Clark

Quoted 46 lines · Dmitry Baryshkov

Quoted 4 lines · Tanmay Shah

From: Chandan Uddaraju <[email protected]>

Add the needed DP PLL specific files to support
display port interface on msm targets.

[skipped]

Review

Quoted 1 line

(quoted diff) +0 -0

b/drivers/gpu/drm/msm/dp/dp_pll_private.h

Quoted 34 lines

new file mode 100644
index 000000000000..475ba6ed59ab

drivers/gpu/drm/msm/dp/dp_pll_private.h new file +29 -0

@@ -0,0 +1,98 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef __DP_PLL_10NM_H
+#define __DP_PLL_10NM_H
+
+#include "dp_pll.h"
+#include "dp_reg.h"
+
+#define DP_VCO_HSCLK_RATE_1620MHZDIV1000    1620000UL
+#define DP_VCO_HSCLK_RATE_2700MHZDIV1000    2700000UL
+#define DP_VCO_HSCLK_RATE_5400MHZDIV1000    5400000UL
+#define DP_VCO_HSCLK_RATE_8100MHZDIV1000    8100000UL
+
+#define NUM_DP_CLOCKS_MAX            6
+
+#define DP_PHY_PLL_POLL_SLEEP_US        500
+#define DP_PHY_PLL_POLL_TIMEOUT_US        10000
+
+#define DP_VCO_RATE_8100MHZDIV1000        8100000UL
+#define DP_VCO_RATE_9720MHZDIV1000        9720000UL
+#define DP_VCO_RATE_10800MHZDIV1000        10800000UL
+
+struct dp_pll_vco_clk {
+    struct clk_hw hw;
+    unsigned long    rate;        /* current vco rate */
+    u64        min_rate;    /* min vco rate */

Quoted 8 lines

drivers/gpu/drm/msm/dp/dp_pll_private.h line 34

Quoted 5 lines

drivers/gpu/drm/msm/dp/dp_pll_private.h new file +5 -0

+    u64        max_rate;    /* max vco rate */
+    void        *priv;
+};
+
+struct dp_pll_db {

This struct should probably go into dp_pll_10nm.c. dp_pll_7nm.c, for example, will use slightly different structure.

Note that sboyd has a WIP series to move all of the pll code out to a phy driver. If there is work already happening on 7nm support, it might be better to go with the separate phy driver approach? I'm still a bit undecided about whether to land the dp code initially with the pll stuff in drm, and then continue refactoring to move to separate phy driver upstream, or to strip out the pll code from the beginning. If you/someone is working on 7nm support, then feedback about which approach is easier is welcome.

Quoted 2 lines

https://lore.kernel.org/dri-devel/[email protected]/

Quoted 8 lines

I have a sm8150/sm8250 (7nm) upstream kernel stack with DP enabled, and I have done something similar, with the PLL driver in the QMP phy, although not based on sboyd's series (along with some typec changes to negotiate the DP alt mode and get HPD events, etc.). I don't think having PLL in drm/msm makes sense, the drm/msm DP driver shouldn't need to be aware of the DP PLL/PHY driver, it only needs to set the link/pixel clock rates which are in dispcc (and those then have the PLL clocks as a parent).

yeah, in the dp case, having phy split out makes a ton of sense.. it would maybe be a nice cleanup in other cases (dsi, hdmi) but the combination of usb+dp makes burying this in drm not so great..

It would be good if you could work w/ sboyd on this.. based on what I've seen on previous gens, it is probably a different phy driver for 7nm vs 10nm, but I think where we want to end up upstream is with phy split out of drm.

Quoted 85 lines · Rob Clark

Quoted 71 lines · Jonathan Marek

Quoted 66 lines · Rob Clark

Quoted 46 lines · Dmitry Baryshkov

Quoted 4 lines · Tanmay Shah

From: Chandan Uddaraju <[email protected]>

Add the needed DP PLL specific files to support
display port interface on msm targets.

[skipped]

Review

Quoted 1 line

(quoted diff) +0 -0

b/drivers/gpu/drm/msm/dp/dp_pll_private.h

Quoted 34 lines

new file mode 100644
index 000000000000..475ba6ed59ab

drivers/gpu/drm/msm/dp/dp_pll_private.h new file +29 -0

@@ -0,0 +1,98 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef __DP_PLL_10NM_H
+#define __DP_PLL_10NM_H
+
+#include "dp_pll.h"
+#include "dp_reg.h"
+
+#define DP_VCO_HSCLK_RATE_1620MHZDIV1000    1620000UL
+#define DP_VCO_HSCLK_RATE_2700MHZDIV1000    2700000UL
+#define DP_VCO_HSCLK_RATE_5400MHZDIV1000    5400000UL
+#define DP_VCO_HSCLK_RATE_8100MHZDIV1000    8100000UL
+
+#define NUM_DP_CLOCKS_MAX            6
+
+#define DP_PHY_PLL_POLL_SLEEP_US        500
+#define DP_PHY_PLL_POLL_TIMEOUT_US        10000
+
+#define DP_VCO_RATE_8100MHZDIV1000        8100000UL
+#define DP_VCO_RATE_9720MHZDIV1000        9720000UL
+#define DP_VCO_RATE_10800MHZDIV1000        10800000UL
+
+struct dp_pll_vco_clk {
+    struct clk_hw hw;
+    unsigned long    rate;        /* current vco rate */
+    u64        min_rate;    /* min vco rate */

Quoted 8 lines

drivers/gpu/drm/msm/dp/dp_pll_private.h line 34

Quoted 5 lines

drivers/gpu/drm/msm/dp/dp_pll_private.h new file +5 -0

+    u64        max_rate;    /* max vco rate */
+    void        *priv;
+};
+
+struct dp_pll_db {

This struct should probably go into dp_pll_10nm.c. dp_pll_7nm.c, for example, will use slightly different structure.

Note that sboyd has a WIP series to move all of the pll code out to a phy driver. If there is work already happening on 7nm support, it might be better to go with the separate phy driver approach? I'm still a bit undecided about whether to land the dp code initially with the pll stuff in drm, and then continue refactoring to move to separate phy driver upstream, or to strip out the pll code from the beginning. If you/someone is working on 7nm support, then feedback about which approach is easier is welcome.

Quoted 2 lines

https://lore.kernel.org/dri-devel/[email protected]/

Quoted 8 lines

I have a sm8150/sm8250 (7nm) upstream kernel stack with DP enabled, and I have done something similar, with the PLL driver in the QMP phy, although not based on sboyd's series (along with some typec changes to negotiate the DP alt mode and get HPD events, etc.). I don't think having PLL in drm/msm makes sense, the drm/msm DP driver shouldn't need to be aware of the DP PLL/PHY driver, it only needs to set the link/pixel clock rates which are in dispcc (and those then have the PLL clocks as a parent).

yeah, in the dp case, having phy split out makes a ton of sense.. it would maybe be a nice cleanup in other cases (dsi, hdmi) but the combination of usb+dp makes burying this in drm not so great..

Quoted 4 lines

It would be good if you could work w/ sboyd on this.. based on what I've seen on previous gens, it is probably a different phy driver for 7nm vs 10nm, but I think where we want to end up upstream is with phy split out of drm.

7nm differs in registers programming, so it would end up with a separate set of tables in qmp phy driver. There is also a 14nm version of dp phy, but I don't know if it usable in any actual hardware design.