mtd: spi-nor: add support for Microchip 25LC256

PATCH In review Radu Pirea 3 participants 11 messages May 4, 2018 – May 18, 2018

Subsystems (2)

Memory technology devices (MTD) SPI NOR

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Radu Pirea

author

2018-05-04 15:53 UTC #0 lore raw

PATCH 1/1 mtd: spi-nor: add support for Microchip 25LC256

Added geometry description for Microchip 25LC256 memory.

Signed-off-by Radu Pirea <[email protected]>

---
 drivers/mtd/devices/m25p80.c  | 3 +++
 drivers/mtd/spi-nor/spi-nor.c | 3 +++
 2 files changed, 6 insertions(+)

drivers/mtd/devices/m25p80.c +3 -0

index a4e18f6aaa33..1e359d811261 100644
@@ -372,6 +372,9 @@ static const struct spi_device_id m25p_ids[] = {
 	{ "mr25h10" },  /*   1 Mib, 40 MHz */
 	{ "mr25h40" },  /*   4 Mib, 40 MHz */
 
+	/* Microchip */
+	{ "25lc256" },
+
 	{ },
 };
 MODULE_DEVICE_TABLE(spi, m25p_ids);

drivers/mtd/spi-nor/spi-nor.c +3 -0

index d445a4d3b770..6341c86be647 100644
@@ -1076,6 +1076,9 @@ static const struct flash_info spi_nor_ids[] = {
 	{ "mx66l1g45g",  INFO(0xc2201b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
 	{ "mx66l1g55g",  INFO(0xc2261b, 0, 64 * 1024, 2048, SPI_NOR_QUAD_READ) },
 
+	/* Microchip */
+	{ "25lc256", CAT25_INFO(32 * 1024, 1, 64, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
+
 	/* Micron */
 	{ "n25q016a",	 INFO(0x20bb15, 0, 64 * 1024,   32, SECT_4K | SPI_NOR_QUAD_READ) },
 	{ "n25q032",	 INFO(0x20ba16, 0, 64 * 1024,   64, SPI_NOR_QUAD_READ) },

Signature · 1 line

2.16.2

Marek Vasut

2018-05-04 17:11 UTC #1 lore raw

Quoted 1 line · Radu Pirea

Added geometry description for Microchip 25LC256 memory.

Are you sure this is a SPI NOR ? I don't see any RDID instruction in the datasheet, only some 6 instructions to read/write the array and lock it. Isn't the AT25 driver a better fit for this EEPROM ?

Quoted 35 lines

Signed-off-by Radu Pirea <[email protected]>

---
 drivers/mtd/devices/m25p80.c  | 3 +++
 drivers/mtd/spi-nor/spi-nor.c | 3 +++
 2 files changed, 6 insertions(+)

drivers/mtd/devices/m25p80.c +3 -0

index a4e18f6aaa33..1e359d811261 100644
@@ -372,6 +372,9 @@ static const struct spi_device_id m25p_ids[] = {
 	{ "mr25h10" },  /*   1 Mib, 40 MHz */
 	{ "mr25h40" },  /*   4 Mib, 40 MHz */
 
+	/* Microchip */
+	{ "25lc256" },
+
 	{ },
 };
 MODULE_DEVICE_TABLE(spi, m25p_ids);

drivers/mtd/spi-nor/spi-nor.c +3 -0

index d445a4d3b770..6341c86be647 100644
@@ -1076,6 +1076,9 @@ static const struct flash_info spi_nor_ids[] = {
 	{ "mx66l1g45g",  INFO(0xc2201b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
 	{ "mx66l1g55g",  INFO(0xc2261b, 0, 64 * 1024, 2048, SPI_NOR_QUAD_READ) },
 
+	/* Microchip */
+	{ "25lc256", CAT25_INFO(32 * 1024, 1, 64, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
+
 	/* Micron */
 	{ "n25q016a",	 INFO(0x20bb15, 0, 64 * 1024,   32, SECT_4K | SPI_NOR_QUAD_READ) },
 	{ "n25q032",	 INFO(0x20ba16, 0, 64 * 1024,   64, SPI_NOR_QUAD_READ) },

Signature · 2 lines

Best regards,
Marek Vasut

Boris Brezillon

2018-05-04 18:40 UTC #2 lore raw

In reply to Radu Pirea

Quoted 1 line · On Fri, 4 May 2018 18:54:04 +0300 Radu Pirea <[email protected]> wrote:

Added geometry description for Microchip 25LC256 memory.

Same as for the dataflash stuff you posted a few weeks ago: I don't think this device belongs in the SPI NOR framework.

Quoted 35 lines

Signed-off-by Radu Pirea <[email protected]>

---
 drivers/mtd/devices/m25p80.c  | 3 +++
 drivers/mtd/spi-nor/spi-nor.c | 3 +++
 2 files changed, 6 insertions(+)

drivers/mtd/devices/m25p80.c +3 -0

index a4e18f6aaa33..1e359d811261 100644
@@ -372,6 +372,9 @@ static const struct spi_device_id m25p_ids[] = {
 	{ "mr25h10" },  /*   1 Mib, 40 MHz */
 	{ "mr25h40" },  /*   4 Mib, 40 MHz */
 
+	/* Microchip */
+	{ "25lc256" },
+
 	{ },
 };
 MODULE_DEVICE_TABLE(spi, m25p_ids);

drivers/mtd/spi-nor/spi-nor.c +3 -0

index d445a4d3b770..6341c86be647 100644
@@ -1076,6 +1076,9 @@ static const struct flash_info spi_nor_ids[] = {
 	{ "mx66l1g45g",  INFO(0xc2201b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
 	{ "mx66l1g55g",  INFO(0xc2261b, 0, 64 * 1024, 2048, SPI_NOR_QUAD_READ) },
 
+	/* Microchip */
+	{ "25lc256", CAT25_INFO(32 * 1024, 1, 64, 2, SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
+
 	/* Micron */
 	{ "n25q016a",	 INFO(0x20bb15, 0, 64 * 1024,   32, SECT_4K | SPI_NOR_QUAD_READ) },
 	{ "n25q032",	 INFO(0x20ba16, 0, 64 * 1024,   64, SPI_NOR_QUAD_READ) },

Radu Pirea

author

2018-05-15 16:20 UTC #3 lore raw

Quoted 7 lines · Boris Brezillon

Quoted 1 line · On Fri, 4 May 2018 18:54:04 +0300 Radu Pirea <[email protected]> wrote:
Added geometry description for Microchip 25LC256 memory.
Same as for the dataflash stuff you posted a few weeks ago: I don't think this device belongs in the SPI NOR framework.

Hi Boris,

25lc256 memory is similar with mr25h256, the only difference is the page size(64 vs 256). Because mr25h256 is already in SPI NOR framework I added here 25lc256.

Quoted 46 lines

Quoted 44 lines
Signed-off-by Radu Pirea <[email protected]>
---
 drivers/mtd/devices/m25p80.c  | 3 +++
 drivers/mtd/spi-nor/spi-nor.c | 3 +++
 2 files changed, 6 insertions(+)
drivers/mtd/devices/m25p80.c +3 -0
index a4e18f6aaa33..1e359d811261 100644
@@ -372,6 +372,9 @@ static const struct spi_device_id m25p_ids[] =
 {
 	{ "mr25h10" },  /*   1 Mib, 40 MHz */
 	{ "mr25h40" },  /*   4 Mib, 40 MHz */
 
+	/* Microchip */
+	{ "25lc256" },
+
 	{ },
 };
MODULE_DEVICE_TABLE(spi, m25p_ids);
drivers/mtd/spi- renamed from drivers/mtd/spi-nor/spi-nor.c +0 -0
nor/spi-nor.c
index d445a4d3b770..6341c86be647 100644
drivers/mtd/spi-nor/spi-nor.c +2 -0
@@ -1076,6 +1076,9 @@ static const struct flash_info spi_nor_ids[]
 = {
 	{ "mx66l1g45g",  INFO(0xc2201b, 0, 64 * 1024, 2048,
 SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
 	{ "mx66l1g55g",  INFO(0xc2261b, 0, 64 * 1024, 2048,
 SPI_NOR_QUAD_READ) },
 
+	/* Microchip */
+	{ "25lc256", CAT25_INFO(32 * 1024, 1, 64, 2,
SPI_NOR_NO_ERASE | SPI_NOR_NO_FR) },
drivers/mtd/spi-nor/spi-nor.c +1 -0
+
 	/* Micron */
 	{ "n25q016a",	 INFO(0x20bb15, 0, 64 * 1024,   32,
SECT_4K | SPI_NOR_QUAD_READ) },
{ "n25q032", INFO(0x20ba16, 0, 64 * 1024, 64,
SPI_NOR_QUAD_READ) },

Marek Vasut

2018-05-15 22:18 UTC #4 lore raw

Quoted 6 lines · Radu Pirea

Quoted 5 lines · Boris Brezillon
Quoted 1 line · On Fri, 4 May 2018 18:54:04 +0300 Radu Pirea <[email protected]> wrote:
Added geometry description for Microchip 25LC256 memory.

Quoted 7 lines

Quoted 2 lines
Same as for the dataflash stuff you posted a few weeks ago: I don't think this device belongs in the SPI NOR framework.
Hi Boris,
25lc256 memory is similar with mr25h256, the only difference is the page size(64 vs 256). Because mr25h256 is already in SPI NOR framework I added here 25lc256.

I think I must be reading the wrong datasheet, but can you show me how does it support things like READID opcode ?

Signature · 2 lines

Best regards,
Marek Vasut

Radu Pirea

author

2018-05-16 10:04 UTC #5 lore raw

Quoted 13 lines · Marek Vasut

Quoted 12 lines · Radu Pirea
Quoted 8 lines · Boris Brezillon
Quoted 1 line · On Fri, 4 May 2018 18:54:04 +0300 Radu Pirea <[email protected]> wrote:
Added geometry description for Microchip 25LC256 memory.
Same as for the dataflash stuff you posted a few weeks ago: I don't
think this device belongs in the SPI NOR framework.
Hi Boris,

Quoted 9 lines

Quoted 4 lines
25lc256 memory is similar with mr25h256, the only difference is the page size(64 vs 256). Because mr25h256 is already in SPI NOR framework
I added here 25lc256.
I think I must be reading the wrong datasheet, but can you show me how
does it support things like READID opcode ?

Hi Marek,

I read the datasheet for 25lc256 and for mr25h256 and none of them supports READID. Is this required for a chip to be included in spi-nor framework? I just followed the mr25h256 as an example.

Marek Vasut

2018-05-16 14:42 UTC #6 lore raw

Quoted 23 lines · Radu Pirea

Quoted 13 lines · Marek Vasut
Quoted 12 lines · Radu Pirea
Quoted 8 lines · Boris Brezillon
Quoted 1 line · On Fri, 4 May 2018 18:54:04 +0300 Radu Pirea <[email protected]> wrote:
Added geometry description for Microchip 25LC256 memory.
Same as for the dataflash stuff you posted a few weeks ago: I don't
think this device belongs in the SPI NOR framework.
Hi Boris,
Quoted 9 lines
Quoted 4 lines
25lc256 memory is similar with mr25h256, the only difference is the page size(64 vs 256). Because mr25h256 is already in SPI NOR framework
I added here 25lc256.
I think I must be reading the wrong datasheet, but can you show me how
does it support things like READID opcode ?

Quoted 5 lines

Hi Marek,
I read the datasheet for 25lc256 and for mr25h256 and none of them supports READID. Is this required for a chip to be included in spi-nor framework? I just followed the mr25h256 as an example.

So I thought until you pointed out the MR25 devices.

Does the 25LC device need erase or not ? I think the MR25s didn't, but I might be wrong.

Maybe the framework could support the 25LC afterall.

Signature · 2 lines

Best regards,
Marek Vasut

Radu Pirea

author

2018-05-18 09:49 UTC #7 lore raw

Quoted 26 lines · Marek Vasut

Quoted 25 lines · Radu Pirea
Quoted 13 lines · Marek Vasut
Quoted 12 lines · Radu Pirea
Quoted 8 lines · Boris Brezillon
Quoted 1 line · On Fri, 4 May 2018 18:54:04 +0300 Radu Pirea <[email protected]> wrote:
Added geometry description for Microchip 25LC256 memory.
Same as for the dataflash stuff you posted a few weeks ago: I don't
think this device belongs in the SPI NOR framework.
Hi Boris,
Quoted 9 lines
Quoted 4 lines
25lc256 memory is similar with mr25h256, the only difference is the page size(64 vs 256). Because mr25h256 is already in SPI NOR framework
I added here 25lc256.
I think I must be reading the wrong datasheet, but can you show me how
does it support things like READID opcode ?
Hi Marek,

Quoted 8 lines

Quoted 3 lines
I read the datasheet for 25lc256 and for mr25h256 and none of them supports READID. Is this required for a chip to be included in spi-nor framework? I just followed the mr25h256 as an example.
So I thought until you pointed out the MR25 devices.
Does the 25LC device need erase or not ? I think the MR25s didn't, but I might be wrong.

You are right. MR25s does not need erase and the same thing is true for 25LC.

Quoted 3 lines

Maybe the framework could support the 25LC afterall.

Yes, this was my impression too.

Thanks.

Marek Vasut

2018-05-18 10:04 UTC #8 lore raw

Quoted 33 lines · Radu Pirea

Quoted 30 lines · Marek Vasut
Quoted 28 lines · Radu Pirea
Quoted 13 lines · Marek Vasut
Quoted 12 lines · Radu Pirea
Quoted 8 lines · Boris Brezillon
Quoted 1 line · On Fri, 4 May 2018 18:54:04 +0300 Radu Pirea <[email protected]> wrote:
Added geometry description for Microchip 25LC256 memory.
Same as for the dataflash stuff you posted a few weeks ago: I don't
think this device belongs in the SPI NOR framework.
Hi Boris,
Quoted 9 lines
Quoted 4 lines
25lc256 memory is similar with mr25h256, the only difference is the page size(64 vs 256). Because mr25h256 is already in SPI NOR framework
I added here 25lc256.
I think I must be reading the wrong datasheet, but can you show me how
does it support things like READID opcode ?
Hi Marek,
I read the datasheet for 25lc256 and for mr25h256 and none of them supports READID. Is this required for a chip to be included in spi-nor framework? I just followed the mr25h256 as an example.

Quoted 7 lines

Quoted 4 lines
So I thought until you pointed out the MR25 devices.
Does the 25LC device need erase or not ? I think the MR25s didn't, but I might be wrong.
You are right. MR25s does not need erase and the same thing is true for 25LC.

Oh. And the command set is (except for readid) comparable to SPI NOR ?

Quoted 3 lines

Quoted 2 lines
Maybe the framework could support the 25LC afterall.
Yes, this was my impression too.

I am still thinking that the AT25 driver might be a better fit for such devices. Can you take a look ?

Signature · 2 lines

Best regards,
Marek Vasut

Radu Pirea

author

2018-05-18 12:59 UTC #9 lore raw

Quoted 42 lines · Marek Vasut

Quoted 33 lines · Radu Pirea
Quoted 30 lines · Marek Vasut
Quoted 28 lines · Radu Pirea
Quoted 13 lines · Marek Vasut
Quoted 12 lines · Radu Pirea
Quoted 8 lines · Boris Brezillon
Quoted 1 line · On Fri, 4 May 2018 18:54:04 +0300 Radu Pirea <[email protected]> wrote:
Added geometry description for Microchip 25LC256 memory.
Same as for the dataflash stuff you posted a few weeks ago: I don't
think this device belongs in the SPI NOR framework.
Hi Boris,
Quoted 9 lines
Quoted 4 lines
25lc256 memory is similar with mr25h256, the only difference is the page size(64 vs 256). Because mr25h256 is already in SPI NOR framework
I added here 25lc256.
I think I must be reading the wrong datasheet, but can you show me how
does it support things like READID opcode ?
Hi Marek,
I read the datasheet for 25lc256 and for mr25h256 and none of them supports READID. Is this required for a chip to be included in spi-nor framework? I just followed the mr25h256 as an example.
Quoted 7 lines
Quoted 4 lines
So I thought until you pointed out the MR25 devices.
Does the 25LC device need erase or not ? I think the MR25s didn't, but I might be wrong.
You are right. MR25s does not need erase and the same thing is true for 25LC.

Quoted 8 lines

Oh. And the command set is (except for readid) comparable to SPI NOR ?
Quoted 3 lines
Quoted 2 lines
Maybe the framework could support the 25LC afterall.
Yes, this was my impression too.
I am still thinking that the AT25 driver might be a better fit for such devices. Can you take a look ?

I tested the memory with at25 driver and it works with no line changed in driver. :)

Quoted 1 line

Marek Vasut

2018-05-18 19:52 UTC #10 lore raw

Quoted 50 lines · Radu Pirea

Quoted 47 lines · Marek Vasut
Quoted 33 lines · Radu Pirea
Quoted 30 lines · Marek Vasut
Quoted 28 lines · Radu Pirea
Quoted 13 lines · Marek Vasut
Quoted 12 lines · Radu Pirea
Quoted 8 lines · Boris Brezillon
Quoted 1 line · On Fri, 4 May 2018 18:54:04 +0300 Radu Pirea <[email protected]> wrote:
Added geometry description for Microchip 25LC256 memory.
Same as for the dataflash stuff you posted a few weeks ago: I don't
think this device belongs in the SPI NOR framework.
Hi Boris,
Quoted 9 lines
Quoted 4 lines
25lc256 memory is similar with mr25h256, the only difference is the page size(64 vs 256). Because mr25h256 is already in SPI NOR framework
I added here 25lc256.
I think I must be reading the wrong datasheet, but can you show me how
does it support things like READID opcode ?
Hi Marek,
I read the datasheet for 25lc256 and for mr25h256 and none of them supports READID. Is this required for a chip to be included in spi-nor framework? I just followed the mr25h256 as an example.
Quoted 8 lines
Quoted 5 lines
So I thought until you pointed out the MR25 devices.
Does the 25LC device need erase or not ? I think the MR25s didn't, but I
might be wrong.
You are right. MR25s does not need erase and the same thing is true for 25LC.
Oh. And the command set is (except for readid) comparable to SPI NOR ?
Quoted 2 lines
Quoted 2 lines
Maybe the framework could support the 25LC afterall.

Quoted 7 lines

Quoted 4 lines
Quoted 1 line
Yes, this was my impression too.
I am still thinking that the AT25 driver might be a better fit for such devices. Can you take a look ?
I tested the memory with at25 driver and it works with no line changed in driver. :)

So AT25 it is then ?

Signature · 2 lines

Best regards,
Marek Vasut