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fpga: Xilinx LogiCore PR Decoupler

PATCH In review Alan Tull 4 participants 7 messages Mar 24, 2017 – Apr 5, 2017

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Alan Tull

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#0 lore raw

cover fpga: Xilinx LogiCore PR Decoupler

Hi Greg,

Please take these two patches for Xilinx LogiCore
PR Decouper for the FPGA bridge framework.

Thanks,
Alan

Moritz Fischer (2):
doc: Add bindings document for Xilinx LogiCore PR Decoupler
fpga: Add support for Xilinx LogiCORE PR Decoupler

 .../bindings/fpga/xilinx-pr-decoupler.txt          |  35 +++++
 drivers/fpga/Kconfig                               |  10 ++
 drivers/fpga/Makefile                              |   1 +
 drivers/fpga/xilinx-pr-decoupler.c                 | 161 +++++++++++++++++++++
 4 files changed, 207 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt
 create mode 100644 drivers/fpga/xilinx-pr-decoupler.c
Signature · 1 line
2.11.0
author
#1 lore raw

PATCH 1/2 doc: Add bindings document for Xilinx LogiCore PR Decoupler

From: Moritz Fischer <[email protected]>

This adds the binding documentation for the Xilinx LogiCORE PR Decoupler soft core.

---
 .../bindings/fpga/xilinx-pr-decoupler.txt          | 35 ++++++++++++++++++++++
 1 file changed, 35 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt
Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt new file +35 -0
new file mode 100644
index 000000000000..2c527ac30398
@@ -0,0 +1,35 @@
+Xilinx LogiCORE Partial Reconfig Decoupler Softcore
+
+The Xilinx LogiCORE Partial Reconfig Decoupler manages one or more
+decouplers / fpga bridges.
+The controller can decouple/disable the bridges which prevents signal
+changes from passing through the bridge.  The controller can also
+couple / enable the bridges which allows traffic to pass through the
+bridge normally.
+
+The Driver supports only MMIO handling. A PR region can have multiple
+PR Decouplers which can be handled independently or chained via decouple/
+decouple_status signals.
+
+Required properties:
+- compatible		: Should contain "xlnx,pr-decoupler-1.00" or "xlnx,pr-decoupler"
+- regs			: base address and size for decoupler module
+- clocks		: input clock to IP
+- clock-names		: should contain "aclk"
+
+Optional properties:
+- bridge-enable		: 0 if driver should disable bridge at startup
+			  1 if driver should enable bridge at startup
+			  Default is to leave bridge in current state.
+
+See Documentation/devicetree/bindings/fpga/fpga-region.txt for generic bindings.
+
+Example:
+	fpga-bridge@100000450 {
+		compatible = "xlnx,pr-decoupler-1.00",
+			     "xlnx-pr-decoupler";
+		regs = <0x10000045 0x10>;
+		clocks = <&clkc 15>;
+		clock-names = "aclk";
+		bridge-enable = <0>;
+	};
Signature · 1 line
2.11.0
maintainer
#2 lore raw

Re: [PATCH 1/2] doc: Add bindings document for Xilinx LogiCore PR Decoupler

Quoted 1 line · Alan Tull

From: Moritz Fischer <[email protected]>

Please use "dt-bindings: fpga: ..." for the subject.

Quoted 7 lines

This adds the binding documentation for the Xilinx LogiCORE PR Decoupler soft core.

I'm confused why you are sending these instead of Moritz? If it goes through you, then it should have your S-o-B too.

Quoted 19 lines
---
 .../bindings/fpga/xilinx-pr-decoupler.txt          | 35 ++++++++++++++++++++++
 1 file changed, 35 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt
Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt new file +5 -0
new file mode 100644
index 000000000000..2c527ac30398
@@ -0,0 +1,35 @@
+Xilinx LogiCORE Partial Reconfig Decoupler Softcore
+
+The Xilinx LogiCORE Partial Reconfig Decoupler manages one or more
+decouplers / fpga bridges.
+The controller can decouple/disable the bridges which prevents signal

Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt line 15

Quoted 10 lines
Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt new file +10 -0
+changes from passing through the bridge.  The controller can also
+couple / enable the bridges which allows traffic to pass through the
+bridge normally.
+
+The Driver supports only MMIO handling. A PR region can have multiple
+PR Decouplers which can be handled independently or chained via decouple/
+decouple_status signals.
+
+Required properties:
+- compatible		: Should contain "xlnx,pr-decoupler-1.00" or "xlnx,pr-decoupler"

I'd drop xlnx,pr-decoupler, but in any case, it should not be OR rather "followed by". Plus the example has both.

Quoted 27 lines
Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt new file +20 -0
+- regs			: base address and size for decoupler module
+- clocks		: input clock to IP
+- clock-names		: should contain "aclk"
+
+Optional properties:
+- bridge-enable		: 0 if driver should disable bridge at startup
+			  1 if driver should enable bridge at startup
+			  Default is to leave bridge in current state.
+
+See Documentation/devicetree/bindings/fpga/fpga-region.txt for generic bindings.
+
+Example:
+	fpga-bridge@100000450 {
+		compatible = "xlnx,pr-decoupler-1.00",
+			     "xlnx-pr-decoupler";
+		regs = <0x10000045 0x10>;
+		clocks = <&clkc 15>;
+		clock-names = "aclk";
+		bridge-enable = <0>;
+	};
Signature · 6 lines
2.11.0

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#3 lore raw

Re: [PATCH 1/2] doc: Add bindings document for Xilinx LogiCore PR Decoupler

Quoted 10 lines · Rob Herring
Quoted 1 line · Alan Tull

From: Moritz Fischer <[email protected]>

Please use "dt-bindings: fpga: ..." for the subject.

Quoted 4 lines

This adds the binding documentation for the Xilinx LogiCORE PR Decoupler soft core.

Quoted 6 lines
Quoted 3 lines

I'm confused why you are sending these instead of Moritz? If it goes through you, then it should have your S-o-B too.

Do you want me to resend this Alan (with Rob's suggestions)?

Quoted 25 lines
Quoted 25 lines
---
 .../bindings/fpga/xilinx-pr-decoupler.txt          | 35 ++++++++++++++++++++++
 1 file changed, 35 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt
Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt new file +10 -0
new file mode 100644
index 000000000000..2c527ac30398
@@ -0,0 +1,35 @@
+Xilinx LogiCORE Partial Reconfig Decoupler Softcore
+
+The Xilinx LogiCORE Partial Reconfig Decoupler manages one or more
+decouplers / fpga bridges.
+The controller can decouple/disable the bridges which prevents signal
+changes from passing through the bridge.  The controller can also
+couple / enable the bridges which allows traffic to pass through the
+bridge normally.
+
+The Driver supports only MMIO handling. A PR region can have multiple
Quoted 8 lines

Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt line 15

Quoted 5 lines
Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt new file +5 -0
+PR Decouplers which can be handled independently or chained via decouple/
+decouple_status signals.
+
+Required properties:
+- compatible : Should contain "xlnx,pr-decoupler-1.00" or "xlnx,pr-decoupler"

I'd drop xlnx,pr-decoupler, but in any case, it should not be OR rather "followed by". Plus the example has both.

Michal wanted to have both, so I put both. Personally I don't care. I think they have some downstream stuff that relied on it.

Quoted 24 lines
Quoted 24 lines
Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt new file +20 -1
+- regs : base address and size for decoupler module
+- clocks : input clock to IP
+- clock-names : should contain "aclk"
+
+Optional properties:
+- bridge-enable : 0 if driver should disable bridge at startup
+  1 if driver should enable bridge at startup
+  Default is to leave bridge in current state.
+
+See Documentation/devicetree/bindings/fpga/fpga-region.txt for generic bindings.
+
+Example:
+ fpga-bridge@100000450 {
+ compatible = "xlnx,pr-decoupler-1.00",
+     "xlnx-pr-decoupler";
+ regs = <0x10000045 0x10>;
+ clocks = <&clkc 15>;
+ clock-names = "aclk";
+ bridge-enable = <0>;
+ };
--

2.11.0

Quoted 4 lines
Quoted 4 lines

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Thanks,
Moritz
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#4 lore raw

Re: [PATCH 1/2] doc: Add bindings document for Xilinx LogiCore PR Decoupler

Quoted 53 lines · Moritz Fischer
Quoted 10 lines · Rob Herring
Quoted 1 line · Alan Tull

From: Moritz Fischer <[email protected]>

Please use "dt-bindings: fpga: ..." for the subject.

Quoted 4 lines

This adds the binding documentation for the Xilinx LogiCORE PR Decoupler soft core.

Quoted 6 lines
Quoted 3 lines

I'm confused why you are sending these instead of Moritz? If it goes through you, then it should have your S-o-B too.

Do you want me to resend this Alan (with Rob's suggestions)?

Quoted 25 lines
Quoted 25 lines
---
 .../bindings/fpga/xilinx-pr-decoupler.txt          | 35 ++++++++++++++++++++++
 1 file changed, 35 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt
Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt new file +10 -0
new file mode 100644
index 000000000000..2c527ac30398
@@ -0,0 +1,35 @@
+Xilinx LogiCORE Partial Reconfig Decoupler Softcore
+
+The Xilinx LogiCORE Partial Reconfig Decoupler manages one or more
+decouplers / fpga bridges.
+The controller can decouple/disable the bridges which prevents signal
+changes from passing through the bridge.  The controller can also
+couple / enable the bridges which allows traffic to pass through the
+bridge normally.
+
+The Driver supports only MMIO handling. A PR region can have multiple
Quoted 8 lines

Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt line 15

Quoted 5 lines
Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt new file +5 -0
+PR Decouplers which can be handled independently or chained via decouple/
+decouple_status signals.
+
+Required properties:
+- compatible : Should contain "xlnx,pr-decoupler-1.00" or "xlnx,pr-decoupler"

I'd drop xlnx,pr-decoupler, but in any case, it should not be OR rather "followed by". Plus the example has both.

Quoted 2 lines

Michal wanted to have both, so I put both. Personally I don't care. I think they have some downstream stuff that relied on it.

Agree with Rob with using "followed by" instead of or.

M

author
#5 lore raw

Re: [PATCH 1/2] doc: Add bindings document for Xilinx LogiCore PR Decoupler

In reply to Moritz Fischer
Quoted 11 lines · Moritz Fischer
Quoted 10 lines · Rob Herring
Quoted 1 line · Alan Tull

From: Moritz Fischer <[email protected]>

Please use "dt-bindings: fpga: ..." for the subject.

Quoted 4 lines

This adds the binding documentation for the Xilinx LogiCORE PR Decoupler soft core.

Quoted 6 lines
Quoted 6 lines
Quoted 3 lines

I'm confused why you are sending these instead of Moritz? If it goes through you, then it should have your S-o-B too.

Greg asked me to send patches to him. I should have started adding my signed-of-by
at that point.

Quoted 2 lines

Do you want me to resend this Alan (with Rob's suggestions)?

I sent a set of patches to Greg on March 24. Looking back on that I realize that it didn't have Rob's ack yet (as well as having my ack where it should have been my signed-of-by).

Yes, please resend this patchset with Rob's feedback.

Thanks,
ALan

Quoted 61 lines
Quoted 25 lines
Quoted 25 lines
---
 .../bindings/fpga/xilinx-pr-decoupler.txt          | 35 ++++++++++++++++++++++
 1 file changed, 35 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt
Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt new file +10 -0
new file mode 100644
index 000000000000..2c527ac30398
@@ -0,0 +1,35 @@
+Xilinx LogiCORE Partial Reconfig Decoupler Softcore
+
+The Xilinx LogiCORE Partial Reconfig Decoupler manages one or more
+decouplers / fpga bridges.
+The controller can decouple/disable the bridges which prevents signal
+changes from passing through the bridge.  The controller can also
+couple / enable the bridges which allows traffic to pass through the
+bridge normally.
+
+The Driver supports only MMIO handling. A PR region can have multiple
Quoted 8 lines

Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt line 15

Quoted 5 lines
Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt new file +5 -0
+PR Decouplers which can be handled independently or chained via decouple/
+decouple_status signals.
+
+Required properties:
+- compatible : Should contain "xlnx,pr-decoupler-1.00" or "xlnx,pr-decoupler"

I'd drop xlnx,pr-decoupler, but in any case, it should not be OR rather "followed by". Plus the example has both.

Michal wanted to have both, so I put both. Personally I don't care. I think they have some downstream stuff that relied on it.

Quoted 24 lines
Quoted 24 lines
Documentation/devicetree/bindings/fpga/xilinx-pr-decoupler.txt new file +20 -1
+- regs : base address and size for decoupler module
+- clocks : input clock to IP
+- clock-names : should contain "aclk"
+
+Optional properties:
+- bridge-enable : 0 if driver should disable bridge at startup
+  1 if driver should enable bridge at startup
+  Default is to leave bridge in current state.
+
+See Documentation/devicetree/bindings/fpga/fpga-region.txt for generic bindings.
+
+Example:
+ fpga-bridge@100000450 {
+ compatible = "xlnx,pr-decoupler-1.00",
+     "xlnx-pr-decoupler";
+ regs = <0x10000045 0x10>;
+ clocks = <&clkc 15>;
+ clock-names = "aclk";
+ bridge-enable = <0>;
+ };
--

2.11.0

Quoted 7 lines
Quoted 4 lines
Quoted 4 lines

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Thanks,
Moritz

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author
#6 lore raw

PATCH 2/2 fpga: Add support for Xilinx LogiCORE PR Decoupler

In reply to Alan Tull

From: Moritz Fischer <[email protected]>

This adds support for the Xilinx LogiCORE PR Decoupler soft-ip that does decoupling of PR regions in the FPGA fabric during partial reconfiguration.

---
 drivers/fpga/Kconfig               |  10 +++
 drivers/fpga/Makefile              |   1 +
 drivers/fpga/xilinx-pr-decoupler.c | 161 +++++++++++++++++++++++++++++++++++++
 3 files changed, 172 insertions(+)
 create mode 100644 drivers/fpga/xilinx-pr-decoupler.c
drivers/fpga/Kconfig +10 -0
index 116ee92fe034..161ba9dccede 100644
@@ -95,6 +95,16 @@ config ALTERA_PR_IP_CORE_PLAT
 	  Platform driver support for Altera Partial Reconfiguration IP
 	  component
 
+config XILINX_PR_DECOUPLER
+	tristate "Xilinx LogiCORE PR Decoupler"
+	depends on FPGA_BRIDGE
+	depends on HAS_IOMEM
+	help
+	  Say Y to enable drivers for Xilinx LogiCORE PR Decoupler.
+	  The PR Decoupler exists in the FPGA fabric to isolate one
+	  region of the FPGA from the busses while that region is
+	  being reprogrammed during partial reconfig.
+
 endif # FPGA
 
 endmenu
drivers/fpga/Makefile +1 -0
index 530cf9410dde..2a4f0218145c 100644
@@ -19,6 +19,7 @@ obj-$(CONFIG_ALTERA_PR_IP_CORE_PLAT)    += altera-pr-ip-core-plat.o
 obj-$(CONFIG_FPGA_BRIDGE)		+= fpga-bridge.o
 obj-$(CONFIG_SOCFPGA_FPGA_BRIDGE)	+= altera-hps2fpga.o altera-fpga2sdram.o
 obj-$(CONFIG_ALTERA_FREEZE_BRIDGE)	+= altera-freeze-bridge.o
+obj-$(CONFIG_XILINX_PR_DECOUPLER)	+= xilinx-pr-decoupler.o
 
 # High Level Interfaces
 obj-$(CONFIG_FPGA_REGION)		+= fpga-region.o
drivers/fpga/xilinx-pr-decoupler.c new file +161 -0

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Signature · 6 lines
2.11.0

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