pinctrl: sunxi: Add A80 Pin Controller support

Hi,

As usual when we support a new SoC, we need to add a new pinctrl driver.

Here is it, this time for the A80, which doesn't bring anything new beside one more bank compared to the previous SoCs, but less pins overall.

Maxime

Maxime Ripard (4):
pinctrl: sunxi: Add PN bank base pin
pinctrl: sunxi: Add A80 pinctrl muxing options
ARM: sun9i: Enable the A80 pinctrl driver
ARM: sun9i: optimus: Set UART0 muxing

 arch/arm/boot/dts/sun9i-a80-optimus.dts   |   2 +
 arch/arm/boot/dts/sun9i-a80.dtsi          |  23 +
 drivers/pinctrl/sunxi/Kconfig             |   4 +
 drivers/pinctrl/sunxi/Makefile            |   1 +
 drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c | 750 ++++++++++++++++++++++++++++++
 drivers/pinctrl/sunxi/pinctrl-sunxi.h     |   1 +
 6 files changed, 781 insertions(+)
 create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c

2.1.1

The A80 R-PIO controller has one more bank that what we've seen so far, add the PN pin bank.

---
 drivers/pinctrl/sunxi/pinctrl-sunxi.h | 1 +
 1 file changed, 1 insertion(+)

index 4245b96c7996..5a51523a3459 100644
@@ -27,6 +27,7 @@
 #define PI_BASE	256
 #define PL_BASE	352
 #define PM_BASE	384
+#define PN_BASE	416
 
 #define SUNXI_PINCTRL_PIN(bank, pin)		\
 	PINCTRL_PIN(P ## bank ## _BASE + (pin), "P" #bank #pin)

2.1.1

The A80 has a rather usual pin controller, the only thing out of the ordinary being that it has 5 interrupts banks, and that some pins have several options for the same functions.

---
 drivers/pinctrl/sunxi/Kconfig             |   4 +
 drivers/pinctrl/sunxi/Makefile            |   1 +
 drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c | 750 ++++++++++++++++++++++++++++++
 3 files changed, 755 insertions(+)
 create mode 100644 drivers/pinctrl/sunxi/pinctrl-sun9i-a80.c

index a5e10f777ed2..230a952608cb 100644
@@ -39,4 +39,8 @@ config PINCTRL_SUN8I_A23_R
 	depends on RESET_CONTROLLER
 	select PINCTRL_SUNXI_COMMON
 
+config PINCTRL_SUN9I_A80
+	def_bool MACH_SUN9I
+	select PINCTRL_SUNXI_COMMON
+
 endif

index e797efb02901..c7d92e4673b5 100644
@@ -10,3 +10,4 @@ obj-$(CONFIG_PINCTRL_SUN6I_A31_R)	+= pinctrl-sun6i-a31-r.o
 obj-$(CONFIG_PINCTRL_SUN7I_A20)		+= pinctrl-sun7i-a20.o
 obj-$(CONFIG_PINCTRL_SUN8I_A23)		+= pinctrl-sun8i-a23.o
 obj-$(CONFIG_PINCTRL_SUN8I_A23_R)	+= pinctrl-sun8i-a23-r.o
+obj-$(CONFIG_PINCTRL_SUN9I_A80)		+= pinctrl-sun9i-a80.o

2.1.1

At Sun, 26 Oct 2014 16:36:04 +0100,

^ Greater-Than missing?

The A80 pinctrl driver is just as usual our pinctrl/gpio/external interrupt controller.

Nothing really out of the extraordinary here...

---
 arch/arm/boot/dts/sun9i-a80.dtsi | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

index 7bcab5685d0e..9616dc71faf3 100644
@@ -337,6 +337,22 @@
 			clocks = <&osc24M>;
 		};
 
+		pio: pinctrl at 06000800 {
+			compatible = "allwinner,sun9i-a80-pinctrl";
+			reg = <0x06000800 0x400>;
+			interrupts = <0 11 4>,
+				     <0 15 4>,
+				     <0 16 4>,
+				     <0 17 4>,
+                                     <0 120 4>;
+			clocks = <&apb0_gates 5>;
+			gpio-controller;
+			interrupt-controller;
+			#interrupt-cells = <2>;
+			#size-cells = <0>;
+			#gpio-cells = <3>;
+		};
+
 		uart0: serial at 07000000 {
 			compatible = "snps,dw-apb-uart";
 			reg = <0x07000000 0x400>;

2.1.1

Hi,

                                     <0 120 4>;

Enable the UART0 muxing, as set up by the bootloader.

---
 arch/arm/boot/dts/sun9i-a80-optimus.dts | 2 ++
 arch/arm/boot/dts/sun9i-a80.dtsi        | 7 +++++++
 2 files changed, 9 insertions(+)

index f83abab108b9..9ed60f3927a3 100644
@@ -60,6 +60,8 @@
 
 	soc {
 		uart0: serial at 07000000 {
+			pinctrl-names = "default";
+			pinctrl-0 = <&uart0_pins_a>;
 			status = "okay";
 		};
 	};

index 9616dc71faf3..29fd38d9fc43 100644
@@ -351,6 +351,13 @@
 			#interrupt-cells = <2>;
 			#size-cells = <0>;
 			#gpio-cells = <3>;
+
+			uart0_pins_a: uart0 at 0 {
+				allwinner,pins = "PH12", "PH13";
+				allwinner,function = "uart0";
+				allwinner,drive = <0>;
+				allwinner,pull = <0>;
+			};
 		};
 
 		uart0: serial at 07000000 {

2.1.1