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add at91 SoC access with c structures

PATCH New Jens Scharsig 1 participant 1 message Dec 19, 2009 Arm/Microchip (AT91) SoC support

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PATCH 4/8 add at91 SoC access with c structures

* prepare AT91RM9200 arch for SoC access update

---
 cpu/arm920t/at91rm9200/bcm5221.c             |    4 ++--
 cpu/arm920t/at91rm9200/dm9161.c              |    3 +--
 cpu/arm920t/at91rm9200/timer.c               |    1 -
 cpu/arm920t/cpu.c                            |    4 ++++
 include/asm-arm/arch-at91rm9200/AT91RM9200.h |   12 ++----------
 5 files changed, 9 insertions(+), 15 deletions(-)
(quoted diff) +0 -0

b/cpu/arm920t/at91rm9200/bcm5221.c
index b52c615..8de3cba 100644

cpu/arm920t/at91rm9200/bcm5221.c +2 -2
@@ -28,10 +28,10 @@
 
 #include <at91rm9200_net.h>
 #include <net.h>
-#include <bcm5221.h>
-
 #ifdef CONFIG_DRIVER_ETHER
 
+#include <bcm5221.h>
+
 #if defined(CONFIG_CMD_NET)
 
 /*
(quoted diff) +0 -0

b/cpu/arm920t/at91rm9200/dm9161.c
index 1beb6e8..6d4384f 100644

cpu/arm920t/at91rm9200/dm9161.c +1 -2
@@ -23,9 +23,8 @@
 
 #include <at91rm9200_net.h>
 #include <net.h>
-#include <dm9161.h>
-
 #ifdef CONFIG_DRIVER_ETHER
+#include <dm9161.h>
 
 #if defined(CONFIG_CMD_NET)
 
cpu/arm920t/at91rm9200/timer.c +0 -1
index 9c54bbe..e4203a6 100644
@@ -33,7 +33,6 @@
 #include <common.h>
 /*#include <asm/io.h>*/
 #include <asm/arch/hardware.h>
-/*#include <asm/proc/ptrace.h>*/
 
 /* the number of clocks per CONFIG_SYS_HZ */
 #define TIMER_LOAD_VAL (CONFIG_SYS_HZ_CLOCK/CONFIG_SYS_HZ)
cpu/arm920t/cpu.c +4 -0
index 34adb11..be82c87 100644
@@ -33,6 +33,10 @@
 #include <command.h>
 #include <asm/system.h>
 
+#ifdef CONFIG_AT91_LEGACY
+#warning Your board is using legacy AT91RM9200 SoC access. Please update!
+#endif
+
 static void cache_flush(void);
 
 int cleanup_before_linux (void)
(quoted diff) +0 -0

b/include/asm-arm/arch-at91rm9200/AT91RM9200.h
index 00bae1c..a04cfa1 100644

include/asm-arm/arch-at91rm9200/AT91RM9200.h +1 -0
@@ -26,6 +26,7 @@
 #define AT91RM9200_H
 
 #ifndef __ASSEMBLY__
+
 typedef volatile unsigned int AT91_REG;		/* Hardware register definition */
 
 /*****************************************************************************/
@@ -749,19 +750,10 @@ typedef struct _AT91S_PDC
 #define AT91C_BASE_PIOC		((AT91PS_PIO)	0xFFFFF800) /* (PIOC) Base

Address */
#define AT91C_BASE_PIOD ((AT91PS_PIO) 0xFFFFFA00) /* (PIOC) Base
Address */
#define AT91C_BASE_PMC ((AT91PS_PMC) 0xFFFFFC00) /* (PMC) Base Address */
-#if 0
-#define AT91C_BASE_ST ((AT91PS_ST) 0xFFFFFD00) /* (PMC) Base Address */
-#define AT91C_BASE_RTC ((AT91PS_RTC) 0xFFFFFE00) /* (PMC) Base Address */
-#define AT91C_BASE_MC ((AT91PS_MC) 0xFFFFFF00) /* (PMC) Base Address */
-#endif

#define AT91C_BASE_TC0 ((AT91PS_TC) 0xFFFA0000) /* (TC0) Base Address */
#define AT91C_BASE_TC1 ((AT91PS_TC) 0xFFFA4000) /* (TC0) Base Address */
-#if 0
-#define AT91C_BASE_UDP ((AT91PS_UDP) 0xFFFB0000) /* (TC0) Base Address */
-#define AT91C_BASE_MCI ((AT91PS_MCI) 0xFFFB4000) /* (TC0) Base Address */
-#define AT91C_BASE_TWI ((AT91PS_TWI) 0xFFFB8000) /* (TC0) Base Address */
-#endif
+
#define AT91C_BASE_EMAC ((AT91PS_EMAC) 0xFFFBC000) /* (EMAC) Base
Address */
#define AT91C_BASE_US0 ((AT91PS_USART) 0xFFFC0000) /* (US0) Base
Address */
#define AT91C_BASE_US1 ((AT91PS_USART) 0xFFFC4000) /* (US1) Base
Address */

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