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OMAP: mmc: add support for second and third mmc channels

RFC PATCH New Steve Sakoman 4 participants 9 messages Apr 29, 2010 – Jun 18, 2010 1 message not in the archive

Subsystems (2)
Arm (32-bit) MMC, SD and SDIO
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Steve Sakoman

author
#0 lore raw

RFC PATCH 1/1 OMAP: mmc: add support for second and third mmc channels

This patch adds support for the second and third mmc channels on OMAP3 processors

Boards wishing to use this feature should define
CONFIG_SYS_MMC_SET_DEV in the board config

Tested on Overo

Signed-off-by Steve Sakoman <[email protected]>

---

(quoted diff) +0 -0

b/arch/arm/include/asm/arch-omap3/mmc_host_def.h
index aa751c9..f081b43 100644

arch/arm/include/asm/arch-omap3/mmc_host_def.h +11 -2
@@ -31,11 +31,18 @@
 typedef struct t2 {
 	unsigned char res1[0x274];
 	unsigned int devconf0;		/* 0x274 */
-	unsigned char res2[0x2A8];
+	unsigned char res2[0x064];
+	unsigned int devconf1;		/* 0x2D8 */
+	unsigned char res3[0x248];
 	unsigned int pbias_lite;	/* 0x520 */
 } t2_t;
 
 #define MMCSDIO1ADPCLKISEL		(1 << 24)
+#define MMCSDIO2ADPCLKISEL		(1 << 6)
+
+#define EN_MMC1				(1 << 24)
+#define EN_MMC2				(1 << 25)
+#define EN_MMC3				(1 << 30)
 
 #define PBIASLITEPWRDNZ0		(1 << 1)
 #define PBIASSPEEDCTRL0			(1 << 2)

@@ -44,7 +51,9 @@ typedef struct t2 {
 /*
  * OMAP HSMMC register definitions
  */
-#define OMAP_HSMMC_BASE		0x4809C000
+#define OMAP_HSMMC1_BASE	0x4809C000
+#define OMAP_HSMMC2_BASE	0x480B4000
+#define OMAP_HSMMC3_BASE	0x480AD000
 
 typedef struct hsmmc {
 	unsigned char res1[0x10];
drivers/mmc/omap3_mmc.c +33 -1
index 96c0e65..bf650ba 100644
@@ -52,7 +52,27 @@ const unsigned short mmc_transspeed_val[15][4] = {
 
 mmc_card_data cur_card_data;
 static block_dev_desc_t mmc_blk_dev;
-static hsmmc_t *mmc_base = (hsmmc_t *)OMAP_HSMMC_BASE;
+static hsmmc_t *mmc_base = (hsmmc_t *)OMAP_HSMMC1_BASE;
+
+unsigned char mmc_set_dev(int dev)
+{
+	switch (dev) {
+	case 1:
+		mmc_base = (hsmmc_t *)OMAP_HSMMC1_BASE;
+		break;
+	case 2:
+		mmc_base = (hsmmc_t *)OMAP_HSMMC2_BASE;
+		break;
+	case 3:
+		mmc_base = (hsmmc_t *)OMAP_HSMMC3_BASE;
+		break;
+	default:
+		mmc_base = (hsmmc_t *)OMAP_HSMMC1_BASE;
+		return 1;
+	}
+
+	return 0;
+}
 
 block_dev_desc_t *mmc_get_dev(int dev)
 {

@@ -62,6 +82,7 @@ block_dev_desc_t *mmc_get_dev(int dev)
 unsigned char mmc_board_init(void)
 {
 	t2_t *t2_base = (t2_t *)T2_BASE;
+	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
 
 #if defined(CONFIG_TWL4030_POWER)
 	twl4030_power_mmc_init();

@@ -74,6 +95,17 @@ unsigned char mmc_board_init(void)
 	writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL,
 		&t2_base->devconf0);
 
+	writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL,
+		&t2_base->devconf1);
+
+	writel(readl(&prcm_base->fclken1_core) |
+		EN_MMC1 | EN_MMC2 | EN_MMC3,
+		&prcm_base->fclken1_core);
+
+	writel(readl(&prcm_base->iclken1_core) |
+		EN_MMC1 | EN_MMC2 | EN_MMC3,
+		&prcm_base->iclken1_core);
+
 	return 1;
 }
 

@@ -512,8 +544,11 @@ unsigned long mmc_bread(int dev_num, unsigned

long blknr, lbaint_t blkcnt,
return 1;
}

-int mmc_legacy_init(int verbose)
+int mmc_legacy_init(int dev)
{
+ if (mmc_set_dev(dev) != 0)
+ return 1;
+
if (configure_mmc(&cur_card_data) != 1)
return 1;

#1 lore raw

RFC PATCH 1/1 OMAP: mmc: add support for second and third mmc channels

Quoted 17 lines · Steve Sakoman

This patch adds support for the second and third mmc channels on OMAP3 processors

Boards wishing to use this feature should define
CONFIG_SYS_MMC_SET_DEV in the board config

Tested on Overo

Signed-off-by Steve Sakoman <[email protected]>

---

arch/arm/include/asm/arch-omap3/mmc_host_def.h +0 -0
index aa751c9..f081b43 100644

arch/arm/include/asm/arch-omap3/mmc_host_def.h line 37

Quoted 8 lines
arch/arm/include/asm/arch-omap3/mmc_host_def.h +3 -1
@@ -31,11 +31,18 @@
 typedef struct t2 {
 	unsigned char res1[0x274];
 	unsigned int devconf0;		/* 0x274 */
-	unsigned char res2[0x2A8];
+	unsigned char res2[0x064];
+	unsigned int devconf1;		/* 0x2D8 */
+	unsigned char res3[0x248];
 	unsigned int pbias_lite;	/* 0x520 */

This changes the offset of pbias_lite -- 0x64+4+0x248 = 0x2b0, not 0x2a8.

The mandatory use of structs even with large reserved areas seems to invite and obscure such issues (and the comments don't help much, since nothing ensures they're accurate).

-Scott

author
#2 lore raw

RFC PATCH 1/1 OMAP: mmc: add support for second and third mmc channels

Quoted 30 lines · Scott Wood
Quoted 20 lines · Steve Sakoman

This patch adds support for the second and third mmc channels on OMAP3 processors

Boards wishing to use this feature should define
CONFIG_SYS_MMC_SET_DEV in the board config

Tested on Overo

Signed-off-by Steve Sakoman <[email protected]>

---

arch/arm/include/asm/arch-omap3/mmc_host_def.h +0 -0
index aa751c9..f081b43 100644
@@ -31,11 +31,18 @@
 ?typedef struct t2 {
 ? ? ? ?unsigned char res1[0x274];
Quoted 6 lines

? ? ? ?unsigned int devconf0; ? ? ? ? ?/* 0x274 */
- ? ? ? unsigned char res2[0x2A8];
+ ? ? ? unsigned char res2[0x064];
+ ? ? ? unsigned int devconf1; ? ? ? ? ?/* 0x2D8 */
+ ? ? ? unsigned char res3[0x248];
? ? ? ?unsigned int pbias_lite; ? ? ? ?/* 0x520 */

This changes the offset of pbias_lite -- 0x64+4+0x248 = 0x2b0, not 0x2a8.

Quoted 3 lines

The mandatory use of structs even with large reserved areas seems to invite and obscure such issues (and the comments don't help much, since nothing ensures they're accurate).

Good catch!

Agreed -- I really hate sparse structs like this since they just invite this type of error when you fill in missing registers.

I'll fix and resubmit the patch for further comment.

Steve

author
#3 lore raw

RFC PATCH 1/1 OMAP: mmc: add support for second and third mmc channels

Quoted 11 lines · Steve Sakoman
Quoted 3 lines · Scott Wood

The mandatory use of structs even with large reserved areas seems to invite and obscure such issues (and the comments don't help much, since nothing ensures they're accurate).

Good catch!

Agreed ?-- I really hate sparse structs like this since they just invite this type of error when you fill in missing registers.

I'll fix and resubmit the patch for further comment.

BTW, the reason I didn't catch this in testing is that the error would only show up for mmc channel 2, which is not available on Overo (it is used for the SDIO wifi interface). My testing was done on mmc1 and mmc2.

Steve

author
#4 lore raw

RFC PATCH v2 1/1 OMAP: mmc: add support for second and third mmc channels

This patch adds support for the second and third mmc channels on OMAP3 processors

Boards wishing to use this feature should define CONFIG_SYS_MMC_SET_DEV

Tested on Overo

Signed-off-by Steve Sakoman <[email protected]>

---

(quoted diff) +0 -0

b/arch/arm/include/asm/arch-omap3/mmc_host_def.h
index aa751c9..f081b43 100644

arch/arm/include/asm/arch-omap3/mmc_host_def.h +11 -2
@@ -31,11 +31,18 @@
 typedef struct t2 {
 	unsigned char res1[0x274];
 	unsigned int devconf0;		/* 0x274 */
-	unsigned char res2[0x2A8];
+	unsigned char res2[0x060];
+	unsigned int devconf1;		/* 0x2D8 */
+	unsigned char res3[0x244];
 	unsigned int pbias_lite;	/* 0x520 */
 } t2_t;
 
 #define MMCSDIO1ADPCLKISEL		(1 << 24)
+#define MMCSDIO2ADPCLKISEL		(1 << 6)
+
+#define EN_MMC1				(1 << 24)
+#define EN_MMC2				(1 << 25)
+#define EN_MMC3				(1 << 30)
 
 #define PBIASLITEPWRDNZ0		(1 << 1)
 #define PBIASSPEEDCTRL0			(1 << 2)

@@ -44,7 +51,9 @@ typedef struct t2 {
 /*
  * OMAP HSMMC register definitions
  */
-#define OMAP_HSMMC_BASE		0x4809C000
+#define OMAP_HSMMC1_BASE	0x4809C000
+#define OMAP_HSMMC2_BASE	0x480B4000
+#define OMAP_HSMMC3_BASE	0x480AD000
 
 typedef struct hsmmc {
 	unsigned char res1[0x10];
drivers/mmc/omap3_mmc.c +33 -1
index 96c0e65..bf650ba 100644
@@ -52,7 +52,27 @@ const unsigned short mmc_transspeed_val[15][4] = {
 
 mmc_card_data cur_card_data;
 static block_dev_desc_t mmc_blk_dev;
-static hsmmc_t *mmc_base = (hsmmc_t *)OMAP_HSMMC_BASE;
+static hsmmc_t *mmc_base = (hsmmc_t *)OMAP_HSMMC1_BASE;
+
+unsigned char mmc_set_dev(int dev)
+{
+	switch (dev) {
+	case 1:
+		mmc_base = (hsmmc_t *)OMAP_HSMMC1_BASE;
+		break;
+	case 2:
+		mmc_base = (hsmmc_t *)OMAP_HSMMC2_BASE;
+		break;
+	case 3:
+		mmc_base = (hsmmc_t *)OMAP_HSMMC3_BASE;
+		break;
+	default:
+		mmc_base = (hsmmc_t *)OMAP_HSMMC1_BASE;
+		return 1;
+	}
+
+	return 0;
+}
 
 block_dev_desc_t *mmc_get_dev(int dev)
 {

@@ -62,6 +82,7 @@ block_dev_desc_t *mmc_get_dev(int dev)
 unsigned char mmc_board_init(void)
 {
 	t2_t *t2_base = (t2_t *)T2_BASE;
+	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
 
 #if defined(CONFIG_TWL4030_POWER)
 	twl4030_power_mmc_init();

@@ -74,6 +95,17 @@ unsigned char mmc_board_init(void)
 	writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL,
 		&t2_base->devconf0);
 
+	writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL,
+		&t2_base->devconf1);
+
+	writel(readl(&prcm_base->fclken1_core) |
+		EN_MMC1 | EN_MMC2 | EN_MMC3,
+		&prcm_base->fclken1_core);
+
+	writel(readl(&prcm_base->iclken1_core) |
+		EN_MMC1 | EN_MMC2 | EN_MMC3,
+		&prcm_base->iclken1_core);
+
 	return 1;
 }
 

@@ -512,8 +544,11 @@ unsigned long mmc_bread(int dev_num, unsigned

long blknr, lbaint_t blkcnt,
return 1;
}

-int mmc_legacy_init(int verbose)
+int mmc_legacy_init(int dev)
{
+ if (mmc_set_dev(dev) != 0)
+ return 1;
+
if (configure_mmc(&cur_card_data) != 1)
return 1;

A message that is not in the archive (sent off-list or not yet received): [email protected]

author
#6 lore raw

RFC PATCH v2 1/1 OMAP: mmc: add support for second and third mmc channels

Quoted 21 lines · Andy Fleming
Quoted 20 lines · Steve Sakoman

This patch adds support for the second and third mmc channels on OMAP3 processors

Boards wishing to use this feature should define CONFIG_SYS_MMC_SET_DEV

Tested on Overo

Signed-off-by Steve Sakoman <[email protected]>

---

arch/arm/include/asm/arch-omap3/mmc_host_def.h +0 -0
index aa751c9..f081b43 100644
@@ -31,11 +31,18 @@
 ?typedef struct t2 {
 ? ? ? ?unsigned char res1[0x274];

? ? ? ?unsigned int devconf0; ? ? ? ? ?/* 0x274 */
- ? ? ? unsigned char res2[0x2A8];

Quoted 8 lines
Quoted 5 lines

+ ? ? ? unsigned char res2[0x060];
+ ? ? ? unsigned int devconf1; ? ? ? ? ?/* 0x2D8 */
+ ? ? ? unsigned char res3[0x244];
? ? ? ?unsigned int pbias_lite; ? ? ? ?/* 0x520 */ ?} t2_t;

Errr...just to make sure, you *meant* to move devconf1, too, right?

Yes! It is used one time to set a "magic" bit that makes the mmc2 channel work. That is why my testing didn't pick up this error -- mmc2 is not available on my hardware, only mmc1 and mmc3. The error with pbias_lite seemed to have no negative effect in my testing!

At any rate, both registers now seem to be correct :-)

Steve

#7 lore raw

RFC PATCH v2 1/1 OMAP: mmc: add support for second and third mmc channels

In reply to Steve Sakoman
Quoted 8 lines · Steve Sakoman

This patch adds support for the second and third mmc channels on OMAP3 processors

Boards wishing to use this feature should define CONFIG_SYS_MMC_SET_DEV

Tested on Overo

Signed-off-by Steve Sakoman<[email protected]>
Tested-by Philip Balister <[email protected]>

Works with mmc3 connected to an over via the TXS0206 level shifter chip.

Philip

Quoted 110 lines

---

arch/arm/include/asm/arch-omap3/mmc_host_def.h +11 -2
index aa751c9..f081b43 100644
@@ -31,11 +31,18 @@
  typedef struct t2 {
  	unsigned char res1[0x274];
  	unsigned int devconf0;		/* 0x274 */
-	unsigned char res2[0x2A8];
+	unsigned char res2[0x060];
+	unsigned int devconf1;		/* 0x2D8 */
+	unsigned char res3[0x244];
  	unsigned int pbias_lite;	/* 0x520 */
  } t2_t;
 
  #define MMCSDIO1ADPCLKISEL		(1<<  24)
+#define MMCSDIO2ADPCLKISEL		(1<<  6)
+
+#define EN_MMC1				(1<<  24)
+#define EN_MMC2				(1<<  25)
+#define EN_MMC3				(1<<  30)
 
  #define PBIASLITEPWRDNZ0		(1<<  1)
  #define PBIASSPEEDCTRL0			(1<<  2)

@@ -44,7 +51,9 @@ typedef struct t2 {
  /*
   * OMAP HSMMC register definitions
   */
-#define OMAP_HSMMC_BASE		0x4809C000
+#define OMAP_HSMMC1_BASE	0x4809C000
+#define OMAP_HSMMC2_BASE	0x480B4000
+#define OMAP_HSMMC3_BASE	0x480AD000
 
  typedef struct hsmmc {
  	unsigned char res1[0x10];
drivers/mmc/omap3_mmc.c +37 -2
index 96c0e65..bf650ba 100644
@@ -52,7 +52,27 @@ const unsigned short mmc_transspeed_val[15][4] = {
 
  mmc_card_data cur_card_data;
  static block_dev_desc_t mmc_blk_dev;
-static hsmmc_t *mmc_base = (hsmmc_t *)OMAP_HSMMC_BASE;
+static hsmmc_t *mmc_base = (hsmmc_t *)OMAP_HSMMC1_BASE;
+
+unsigned char mmc_set_dev(int dev)
+{
+	switch (dev) {
+	case 1:
+		mmc_base = (hsmmc_t *)OMAP_HSMMC1_BASE;
+		break;
+	case 2:
+		mmc_base = (hsmmc_t *)OMAP_HSMMC2_BASE;
+		break;
+	case 3:
+		mmc_base = (hsmmc_t *)OMAP_HSMMC3_BASE;
+		break;
+	default:
+		mmc_base = (hsmmc_t *)OMAP_HSMMC1_BASE;
+		return 1;
+	}
+
+	return 0;
+}
 
  block_dev_desc_t *mmc_get_dev(int dev)
  {

@@ -62,6 +82,7 @@ block_dev_desc_t *mmc_get_dev(int dev)
  unsigned char mmc_board_init(void)
  {
  	t2_t *t2_base = (t2_t *)T2_BASE;
+	struct prcm *prcm_base = (struct prcm *)PRCM_BASE;
 
  #if defined(CONFIG_TWL4030_POWER)
  	twl4030_power_mmc_init();

@@ -74,6 +95,17 @@ unsigned char mmc_board_init(void)
  	writel(readl(&t2_base->devconf0) | MMCSDIO1ADPCLKISEL,
  		&t2_base->devconf0);
 
+	writel(readl(&t2_base->devconf1) | MMCSDIO2ADPCLKISEL,
+		&t2_base->devconf1);
+
+	writel(readl(&prcm_base->fclken1_core) |
+		EN_MMC1 | EN_MMC2 | EN_MMC3,
+		&prcm_base->fclken1_core);
+
+	writel(readl(&prcm_base->iclken1_core) |
+		EN_MMC1 | EN_MMC2 | EN_MMC3,
+		&prcm_base->iclken1_core);
+
  	return 1;
  }
 

@@ -512,8 +544,11 @@ unsigned long mmc_bread(int dev_num, unsigned
 long blknr, lbaint_t blkcnt,
  	return 1;
  }
 
-int mmc_legacy_init(int verbose)
+int mmc_legacy_init(int dev)
  {
+	if (mmc_set_dev(dev) != 0)
+		return 1;
+
  	if (configure_mmc(&cur_card_data) != 1)
  		return 1;
Applied
#8 lore raw

RFC PATCH v2 1/1 OMAP: mmc: add support for second and third mmc channels

In reply to Steve Sakoman
Quoted 8 lines · Steve Sakoman

This patch adds support for the second and third mmc channels on OMAP3 processors

Boards wishing to use this feature should define CONFIG_SYS_MMC_SET_DEV

Tested on Overo

Signed-off-by Steve Sakoman <[email protected]>

Applied, thanks!

author
#9 lore raw

RFC PATCH v2 1/1 OMAP: mmc: add support for second and third mmc channels

Quoted 11 lines · Andy Fleming
Quoted 8 lines · Steve Sakoman

This patch adds support for the second and third mmc channels on OMAP3 processors

Boards wishing to use this feature should define CONFIG_SYS_MMC_SET_DEV

Tested on Overo

Signed-off-by Steve Sakoman <[email protected]>

Applied, thanks!

I can't seem to find which branch this has been applied to!

I have a new patch series which depends on this. Do I need to resubmit?

Regards,

Steve