board/t104xrdb: Add support of NAND, SD, SPI boot for T104xRDB
PATCH v2 10/10 board/t104xrdb: Add support of NAND, SD, SPI boot for T104xRDB
Add support of 2 stage NAND, SD, SPI boot loader using SPL framework. here, PBL initialise the internal SRAM and copy SPL(160KB). This further initialise DDR using SPD and environment and copy u-boot(768 KB) from NAND to DDR. Finally SPL transer control to u-boot.
Initialise/create followings required for SPL framework
- Add spl.c which defines board_init_f, board_init_r
- update tlb and ddr accordingly
---
This patch depends upon
A) [PATCH 3] powerpc/t104xrdb: Unification of T104xRDB header files
http://patchwork.ozlabs.org/patch/335207/
B) [U-Boot,v5] board/t104xrdb: Add support of CPLD
http://patchwork.ozlabs.org/patch/336616/
Changes for v2:
- Updated defines of SPL
- Updated SPL to load env from SPI, MMC to CPC
- Updated NAND FW, QE FMAN address
board/freescale/t104xrdb/Makefile | 7 +- board/freescale/t104xrdb/README | 73 ++++++++++++++++++ board/freescale/t104xrdb/ddr.c | 5 +- board/freescale/t104xrdb/spl.c | 122 ++++++++++++++++++++++++++++++ board/freescale/t104xrdb/t1040_rcw.cfg | 7 ++ board/freescale/t104xrdb/t1042_rcw.cfg | 7 ++ board/freescale/t104xrdb/t104x_pbi.cfg | 26 +++++++ board/freescale/t104xrdb/tlb.c | 12 +++ boards.cfg | 6 ++ include/configs/T104xRDB.h | 127 +++++++++++++++++++++++++++----- 10 files changed, 372 insertions(+), 20 deletions(-) create mode 100644 board/freescale/t104xrdb/spl.c create mode 100644 board/freescale/t104xrdb/t1040_rcw.cfg create mode 100644 board/freescale/t104xrdb/t1042_rcw.cfg create mode 100644 board/freescale/t104xrdb/t104x_pbi.cfg
board/freescale/t104xrdb/Makefile +5 -2
@@ -4,11 +4,14 @@ # SPDX-License-Identifier: GPL-2.0+ # - +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +else obj-y += t104xrdb.o obj-y += cpld.o -obj-y += ddr.o obj-y += eth.o obj-$(CONFIG_PCI) += pci.o +endif +obj-y += ddr.o obj-y += law.o obj-y += tlb.o
board/freescale/t104xrdb/README +73 -0
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board/freescale/t104xrdb/ddr.c +4 -1
@@ -113,6 +113,7 @@ phys_size_t initdram(int board_type) {phys_size_t dram_size; +#if defined(CONFIG_SPL_BUILD ) || !defined(CONFIG_RAMBOOT_PBL )puts ("Initializing....using SPD\n" ); dram_size =fsl_ddr_sdram ();
@@ -120,6 +121,8 @@ phys_size_t initdram(int board_type) dram_size =setup_ddr_tlbs (dram_size /0x100000 ); dram_size *=0x100000 ; -puts (" DDR: " ); +#else + dram_size =fsl_ddr_sdram_size (); +#endif return dram_size; }
board/freescale/t104xrdb/spl.c new file +122 -0
122 lines not on this page · raw message
board/freescale/t104xrdb/t1040_rcw.cfg new file +7 -0
@@ -0,0 +1,7 @@ +#PBL preamble and RCW header +aa55aa55 010e0100 +# serdes protocol 0x66 +0c18000e 0e000000 00000000 00000000 +66000002 80000002 e8106000 01000000 +00000000 00000000 00000000 00032810 +00000000 0342500f 00000000 00000000
board/freescale/t104xrdb/t1042_rcw.cfg new file +7 -0
@@ -0,0 +1,7 @@ +#PBL preamble and RCW header +aa55aa55 010e0100 +# serdes protocol 0x66 +0c18000e 0e000000 00000000 00000000 +06000002 00400002 e8106000 01000000 +00000000 00000000 00000000 00030810 +00000000 01fe0a06 00000000 00000000
board/freescale/t104xrdb/t104x_pbi.cfg new file +26 -0
@@ -0,0 +1,26 @@ +#PBI commands +#Initialize CPC1 +09010000 00200400 +09138000 00000000 +091380c0 00000100 +#Configure CPC1 as 256KB SRAM +09010100 00000000 +09010104 fffc0007 +09010f00 08000000 +09010000 80000000 +#Configure LAW for CPC1 +09000cd0 00000000 +09000cd4 fffc0000 +09000cd8 81000011 +#Configure alternate space +09000010 00000000 +09000014 ff000000 +09000018 81000000 +#Configure SPI controller +09110000 80000403 +09110020 2d170008 +09110024 00100008 +09110028 00100008 +0911002c 00100008 +#Flush PBL data +091380c0 000FFFFF
board/freescale/t104xrdb/tlb.c +12 -0
@@ -53,6 +53,7 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, 0, 2, BOOKE_PAGESZ_256M, 1), +#ifndef CONFIG_SPL_BUILD /* *I*G* - PCI */ SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
@@ -82,6 +83,7 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 8, BOOKE_PAGESZ_16M, 1),#endif +#endif #ifdef CONFIG_SYS_DCSRBAR_PHYS SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
@@ -102,6 +104,16 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 11, BOOKE_PAGESZ_256K, 1),#endif + +#if defined(CONFIG_RAMBOOT_PBL ) && !defined(CONFIG_SPL_BUILD ) +SET_TLB_ENTRY (1 ,CONFIG_SYS_DDR_SDRAM_BASE ,CONFIG_SYS_DDR_SDRAM_BASE , +MAS3_SX |MAS3_SW |MAS3_SR ,0 , +0 ,12 ,BOOKE_PAGESZ_1G ,1 ), +SET_TLB_ENTRY (1 ,CONFIG_SYS_DDR_SDRAM_BASE +0x40000000 , +CONFIG_SYS_DDR_SDRAM_BASE +0x40000000 , +MAS3_SX |MAS3_SW |MAS3_SR ,0 , + 0, 13, BOOKE_PAGESZ_1G, 1) +#endif };int num_tlb_entries =ARRAY_SIZE (tlb_table);
boards.cfg +6 -0
@@ -933,7 +933,13 @@ Active powerpc mpc85xx - freescale p2041rdb Active powerpc mpc85xx - freescale p2041rdb P2041RDB_SRIO_PCIE_BOOT P2041RDB:SRIO_PCIE_BOOT_SLAVE,SYS_TEXT_BASE=0xFFF40000 - Active powerpc mpc85xx - freescale t1040qds T1040QDS T1040QDS:PPC_T1040 Poonam Aggrwal <[email protected]> Active powerpc mpc85xx - freescale t104xrdb T1040RDB T104xRDB:PPC_T1040,T1040RDB Priyanka Jain <[email protected]> +Active powerpc mpc85xx - freescale t104xrdb T1040RDB_NAND T104xRDB:PPC_T1040,T1040RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND Priyanka Jain <[email protected]> +Active powerpc mpc85xx - freescale t104xrdb T1040RDB_SPIFLASH T104xRDB:PPC_T1040,T1040RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH Priyanka Jain <[email protected]> +Active powerpc mpc85xx - freescale t104xrdb T1040RDB_SDCARD T104xRDB:PPC_T1040,T1040RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD Active powerpc mpc85xx - freescale t104xrdb T1042RDB_PI T104xRDB:PPC_T1042,T1042RDB_PI Priyanka Jain <[email protected]> +Active powerpc mpc85xx - freescale t104xrdb T1042RDB_PI_NAND T104xRDB:PPC_T1042,T1042RDB_PI,RAMBOOT_PBL,SPL_FSL_PBL,NAND Priyanka Jain <[email protected]> +Active powerpc mpc85xx - freescale t104xrdb T1042RDB_PI_SPIFLASH T104xRDB:PPC_T1042,T1042RDB_PI,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH Priyanka Jain <[email protected]> +Active powerpc mpc85xx - freescale t104xrdb T1042RDB_PI_SDCARD T104xRDB:PPC_T1042,T1042RDB_PI,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD Active powerpc mpc85xx - freescale t208xqds T2080QDS T208xQDS:PPC_T2080 - Active powerpc mpc85xx - freescale t208xqds T2080QDS_NAND T208xQDS:PPC_T2080,RAMBOOT_PBL,NAND,SYS_TEXT_BASE=0xFFF40000 - Active powerpc mpc85xx - freescale t208xqds T2080QDS_SDCARD T208xQDS:PPC_T2080,RAMBOOT_PBL,SDCARD,SYS_TEXT_BASE=0xFFF40000 -
include/configs/T104xRDB.h +110 -17
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Signature · 1 line
1.7.9.5
PATCH v2 10/10 board/t104xrdb: Add support of NAND, SD, SPI boot for T104xRDB
Dear Prabhakar Kushwaha,
Quoted 4 lines · Prabhakar Kushwaha <prabhakar <at> freescale.com> writes:
Add support of 2 stage NAND, SD, SPI boot loader using SPL framework. here, PBL initialise the internal SRAM and copy SPL(160KB). This further initialise DDR using SPD and environment and copy u-boot(768 KB) from NAND
to DDR.
Quoted 7 lines
Finally SPL transer control to u-boot.
Initialise/create followings required for SPL framework
- Addspl.cwhich definesboard_init_f,board_init_r
- update tlb and ddr accordinglySigned-off-by Prabhakar Kushwaha <prabhakar <at> freescale.com>
I've copied these modifications and changed them for T1040QDS (it's the only board I have). SPL boot does not proceed.
SPL stops in spi_xfer() during spi_spl_load_image(). The Data TLB error seems to be caused by an stbx but the register operands contain zeroes. SPL hangs with a Data TLB error at this time CPC-SRAM is also corrupted. There are 4-bytes mangled in the [U-boot SPL] area.
Original:
0000000: 27051956 552d426f 6f742032 3031332e '..VU-Boot 2013.
After:
0000000: 27051956 fffd9584 6f742032 3031332e '..V....ot 2013.
fffd9584 is the address of trap_init().
These errors also occurs in u-boot-fsl-qoriq tree (2014.04). Tried different compilers from ELDK 5.3, ELDK 5.4 to FSL 1.2. Any ideas on the cause of these errors?
All the best,
Rommel