add support for more devices on Meson8 and Meson8b
Subsystems (4)
Martin Blumenstingl
reviewercover add support for more devices on Meson8 and Meson8b
This series adds:
- USB support on Meson8 and Meson8b (it seems that some boards show an error when trying to initialize one of the USB2 PHYs, but we have the same problem on some GXBB boards. it is working fine for me - on a board which is not supported upstream yet)
- hardware random number generator support (Meson8 and Meson8b seem to have two 32-bit hardware random number generator registers, while the GX SoCs only have one. This is not handled by the meson-rng driver yet, but that can still be improved later on)
- SAR ADC support
- add reserved memory zones to fix random hangs when filling the memory (currently only on Meson8 until I have a Meson8b device to test if the same problem appears there as well)
- use the real ethernet clock on Meson8 and Meson8b to fix ethernet when the bootloader does not enable the gate clock
- add the SCU (Snoop Control Unit) which is needed for SMP support
- minor preparations for further .dts updates as this already exports the SDIO clocks (a driver for this MMC controller is work-in-progress) as well as the corresponding pin definitions in meson8.dtsi
- this adds the pwm_e (typically used for the 32.768 kHz LPO clock for the SDIO wifi chip) and pwm_f (used on some boards for the dimmable power LED) pins to meson8.dtsi
NOTE: the .dts changes from this series depend on my previous patch from [0]: "ARM: dts: meson8: fix the IR receiver pins"
[0] http://lists.infradead.org/pipermail/linux-amlogic/2017-June/003983.html
Martin Blumenstingl (13):
clk: meson8b: export the SAR ADC clocks
clk: meson8b: export the SDIO clock
clk: meson8b: export the gate clock for the HW random number generator
clk: meson8b: export the USB clocks
clk: meson8b: export the ethernet gate clock
ARM: dts: meson8: add the PWM_E and PWM_F pins
ARM: dts: meson8: add the pins for the SDIO controller
ARM: dts: meson: add the SAR ADC
ARM: dts: meson8: add reserved memory zones
ARM: dts: meson: add the hardware random number generator
ARM: dts: meson: add USB support on Meson8 and Meson8b
ARM: dts: meson8b: add the SCU device node
ARM: dts: meson: use the real ethernet clock on Meson8 and Meson8b
arch/arm/boot/dts/meson.dtsi | 51 +++++++++++++++ arch/arm/boot/dts/meson8.dtsi | 109 ++++++++++++++++++++++++++++++- arch/arm/boot/dts/meson8b.dtsi | 49 ++++++++++++++ drivers/clk/meson/meson8b.h | 20 +++--- include/dt-bindings/clock/meson8b-clkc.h | 10 +++ 5 files changed, 228 insertions(+), 11 deletions(-)
Signature · 1 line
2.13.1
Martin Blumenstingl
reviewerPATCH 1/13 clk: meson8b: export the SAR ADC clocks
Export the clocks for the SAR ADC so they can be used in the dt-bindings.
--- drivers/clk/meson/meson8b.h | 4 ++-- include/dt-bindings/clock/meson8b-clkc.h | 2 ++ 2 files changed, 4 insertions(+), 2 deletions(-)
drivers/clk/meson/meson8b.h +2 -2
@@ -87,7 +87,7 @@#define CLKID_PERIPHS 20#define CLKID_SPICC 21#define CLKID_I2C 22 -#define CLKID_SAR_ADC 23 +/* #define CLKID_SAR_ADC */ #define CLKID_SMART_CARD 24#define CLKID_RNG0 25#define CLKID_UART0 26
@@ -133,7 +133,7 @@#define CLKID_MMC_PCLK 66#define CLKID_DVIN 67#define CLKID_UART2 68 -#define CLKID_SANA 69 +/* #define CLKID_SANA */ #define CLKID_VPU_INTR 70#define CLKID_SEC_AHB_AHB3_BRIDGE 71#define CLKID_CLK81_A9 72
include/dt-bindings/clock/meson8b-clkc.h +2 -0
@@ -21,5 +21,7 @@#define CLKID_ZERO 13#define CLKID_MPEG_SEL 14#define CLKID_MPEG_DIV 15 +#define CLKID_SAR_ADC 23 +#define CLKID_SANA 69#endif /* __MESON8B_CLKC_H */
Signature · 1 line
2.13.1
PATCH 1/13 clk: meson8b: export the SAR ADC clocks
Quoted 37 lines · Martin Blumenstingl
Export the clocks for the SAR ADC so they can be used in the dt-bindings.
Signed-off-by Martin Blumenstingl <[email protected]>--- drivers/clk/meson/meson8b.h | 4 ++-- include/dt-bindings/clock/meson8b-clkc.h | 2 ++ 2 files changed, 4 insertions(+), 2 deletions(-)drivers/clk/meson/meson8b.h +2
-2@@ -87,7 +87,7 @@#define CLKID_PERIPHS 20#define CLKID_SPICC 21#define CLKID_I2C 22 -#define CLKID_SAR_ADC 23 +/* #define CLKID_SAR_ADC */ #define CLKID_SMART_CARD 24#define CLKID_RNG0 25#define CLKID_UART0 26@@ -133,7 +133,7 @@#define CLKID_MMC_PCLK 66#define CLKID_DVIN 67#define CLKID_UART2 68 -#define CLKID_SANA 69 +/* #define CLKID_SANA */ #define CLKID_VPU_INTR 70#define CLKID_SEC_AHB_AHB3_BRIDGE 71#define CLKID_CLK81_A9 72include/dt-bindings/clock/meson8b-clkc.h +0
-0
include/dt-bindings/clock/meson8b-clkc.h line 27
Quoted 7 lines
include/dt-bindings/clock/meson8b-clkc.h +2
-0@@ -21,5 +21,7 @@#define CLKID_ZERO 13#define CLKID_MPEG_SEL 14#define CLKID_MPEG_DIV 15 +#define CLKID_SAR_ADC 23 +#define CLKID_SANA 69#endif /* __MESON8B_CLKC_H */
Martin Blumenstingl
reviewerPATCH 2/13 clk: meson8b: export the SDIO clock
In reply to Martin BlumenstinglExport the SDIO clock so it can be used in the dt-bindings.
--- drivers/clk/meson/meson8b.h | 2 +- include/dt-bindings/clock/meson8b-clkc.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-)
drivers/clk/meson/meson8b.h +1 -1
@@ -94,7 +94,7 @@#define CLKID_SDHC 27#define CLKID_STREAM 28#define CLKID_ASYNC_FIFO 29 -#define CLKID_SDIO 30 +/* #define CLKID_SDIO */ #define CLKID_ABUF 31#define CLKID_HIU_IFACE 32#define CLKID_ASSIST_MISC 33
include/dt-bindings/clock/meson8b-clkc.h +1 -0
@@ -22,6 +22,7 @@#define CLKID_MPEG_SEL 14#define CLKID_MPEG_DIV 15#define CLKID_SAR_ADC 23 +#define CLKID_SDIO 30#define CLKID_SANA 69#endif /* __MESON8B_CLKC_H */
Signature · 1 line
2.13.1
PATCH 2/13 clk: meson8b: export the SDIO clock
Quoted 27 lines · Martin Blumenstingl
Export the SDIO clock so it can be used in the dt-bindings.
Signed-off-by Martin Blumenstingl <[email protected]>--- drivers/clk/meson/meson8b.h | 2 +- include/dt-bindings/clock/meson8b-clkc.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-)drivers/clk/meson/meson8b.h +1
-1@@ -94,7 +94,7 @@#define CLKID_SDHC 27#define CLKID_STREAM 28#define CLKID_ASYNC_FIFO 29 -#define CLKID_SDIO 30 +/* #define CLKID_SDIO */ #define CLKID_ABUF 31#define CLKID_HIU_IFACE 32#define CLKID_ASSIST_MISC 33include/dt-bindings/clock/meson8b-clkc.h +0
-0
include/dt-bindings/clock/meson8b-clkc.h line 28
Quoted 7 lines
include/dt-bindings/clock/meson8b-clkc.h +1
-0@@ -22,6 +22,7 @@#define CLKID_MPEG_SEL 14#define CLKID_MPEG_DIV 15#define CLKID_SAR_ADC 23 +#define CLKID_SDIO 30#define CLKID_SANA 69#endif /* __MESON8B_CLKC_H */
Martin Blumenstingl
reviewerPATCH 3/13 clk: meson8b: export the gate clock for the HW random number generator
In reply to Martin BlumenstinglThis exports the clock so it can be used in the dt-bindings.
--- drivers/clk/meson/meson8b.h | 2 +- include/dt-bindings/clock/meson8b-clkc.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-)
drivers/clk/meson/meson8b.h +1 -1
@@ -89,7 +89,7 @@#define CLKID_I2C 22/* #define CLKID_SAR_ADC */ #define CLKID_SMART_CARD 24 -#define CLKID_RNG0 25 +/* #define CLKID_RNG0 */ #define CLKID_UART0 26#define CLKID_SDHC 27#define CLKID_STREAM 28
include/dt-bindings/clock/meson8b-clkc.h +1 -0
@@ -22,6 +22,7 @@#define CLKID_MPEG_SEL 14#define CLKID_MPEG_DIV 15#define CLKID_SAR_ADC 23 +#define CLKID_RNG0 25#define CLKID_SDIO 30#define CLKID_SANA 69
Signature · 1 line
2.13.1
PATCH 3/13 clk: meson8b: export the gate clock for the HW random number generator
Quoted 27 lines · Martin Blumenstingl
This exports the clock so it can be used in the dt-bindings.
Signed-off-by Martin Blumenstingl <[email protected]>--- drivers/clk/meson/meson8b.h | 2 +- include/dt-bindings/clock/meson8b-clkc.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-)drivers/clk/meson/meson8b.h +1
-1@@ -89,7 +89,7 @@#define CLKID_I2C 22/* #define CLKID_SAR_ADC */ #define CLKID_SMART_CARD 24 -#define CLKID_RNG0 25 +/* #define CLKID_RNG0 */ #define CLKID_UART0 26#define CLKID_SDHC 27#define CLKID_STREAM 28include/dt-bindings/clock/meson8b-clkc.h +0
-0
include/dt-bindings/clock/meson8b-clkc.h line 28
Quoted 7 lines
include/dt-bindings/clock/meson8b-clkc.h +1
-0@@ -22,6 +22,7 @@#define CLKID_MPEG_SEL 14#define CLKID_MPEG_DIV 15#define CLKID_SAR_ADC 23 +#define CLKID_RNG0 25#define CLKID_SDIO 30#define CLKID_SANA 69
Martin Blumenstingl
reviewerPATCH 4/13 clk: meson8b: export the USB clocks
In reply to Martin BlumenstinglExport the USB related clocks (for the USB controller and the USB2 PHYs) so they can be used in the dt-bindings.
--- drivers/clk/meson/meson8b.h | 10 +++++----- include/dt-bindings/clock/meson8b-clkc.h | 5 +++++ 2 files changed, 10 insertions(+), 5 deletions(-)
drivers/clk/meson/meson8b.h +5 -5
@@ -114,12 +114,12 @@#define CLKID_AIU 47#define CLKID_UART1 48#define CLKID_G2D 49 -#define CLKID_USB0 50 -#define CLKID_USB1 51 +/* #define CLKID_USB0 */ +/* #define CLKID_USB1 */ #define CLKID_RESET 52#define CLKID_NAND 53#define CLKID_DOS_PARSER 54 -#define CLKID_USB 55 +/* #define CLKID_USB */ #define CLKID_VDIN1 56#define CLKID_AHB_ARB0 57#define CLKID_EFUSE 58
@@ -128,8 +128,8 @@#define CLKID_AHB_CTRL_BUS 61#define CLKID_HDMI_INTR_SYNC 62#define CLKID_HDMI_PCLK 63 -#define CLKID_USB1_DDR_BRIDGE 64 -#define CLKID_USB0_DDR_BRIDGE 65 +/* CLKID_USB1_DDR_BRIDGE */ +/* CLKID_USB0_DDR_BRIDGE */ #define CLKID_MMC_PCLK 66#define CLKID_DVIN 67#define CLKID_UART2 68
include/dt-bindings/clock/meson8b-clkc.h +5 -0
@@ -24,6 +24,11 @@#define CLKID_SAR_ADC 23#define CLKID_RNG0 25#define CLKID_SDIO 30 +#define CLKID_USB0 50 +#define CLKID_USB1 51 +#define CLKID_USB 55 +#define CLKID_USB1_DDR_BRIDGE 64 +#define CLKID_USB0_DDR_BRIDGE 65#define CLKID_SANA 69#endif /* __MESON8B_CLKC_H */
Signature · 1 line
2.13.1
PATCH 4/13 clk: meson8b: export the USB clocks
Quoted 47 lines · Martin Blumenstingl
Export the USB related clocks (for the USB controller and the USB2 PHYs) so they can be used in the dt-bindings.
Signed-off-by Martin Blumenstingl <[email protected]>--- drivers/clk/meson/meson8b.h | 10 +++++----- include/dt-bindings/clock/meson8b-clkc.h | 5 +++++ 2 files changed, 10 insertions(+), 5 deletions(-)drivers/clk/meson/meson8b.h +5
-5@@ -114,12 +114,12 @@#define CLKID_AIU 47#define CLKID_UART1 48#define CLKID_G2D 49 -#define CLKID_USB0 50 -#define CLKID_USB1 51 +/* #define CLKID_USB0 */ +/* #define CLKID_USB1 */ #define CLKID_RESET 52#define CLKID_NAND 53#define CLKID_DOS_PARSER 54 -#define CLKID_USB 55 +/* #define CLKID_USB */ #define CLKID_VDIN1 56#define CLKID_AHB_ARB0 57#define CLKID_EFUSE 58@@ -128,8 +128,8 @@#define CLKID_AHB_CTRL_BUS 61#define CLKID_HDMI_INTR_SYNC 62#define CLKID_HDMI_PCLK 63 -#define CLKID_USB1_DDR_BRIDGE 64 -#define CLKID_USB0_DDR_BRIDGE 65 +/* CLKID_USB1_DDR_BRIDGE */ +/* CLKID_USB0_DDR_BRIDGE */ #define CLKID_MMC_PCLK 66#define CLKID_DVIN 67#define CLKID_UART2 68include/dt-bindings/clock/meson8b-clkc.h +0
-0@@ -24,6 +24,11 @@#define CLKID_SAR_ADC 23
include/dt-bindings/clock/meson8b-clkc.h line 34
Quoted 10 lines
include/dt-bindings/clock/meson8b-clkc.h +5
-0#define CLKID_RNG0 25#define CLKID_SDIO 30 +#define CLKID_USB0 50 +#define CLKID_USB1 51 +#define CLKID_USB 55 +#define CLKID_USB1_DDR_BRIDGE 64 +#define CLKID_USB0_DDR_BRIDGE 65#define CLKID_SANA 69#endif /* __MESON8B_CLKC_H */
Martin Blumenstingl
reviewerPATCH 5/13 clk: meson8b: export the ethernet gate clock
In reply to Martin BlumenstinglExport the ethernet gate clock to the dt-bindings.
--- drivers/clk/meson/meson8b.h | 2 +- include/dt-bindings/clock/meson8b-clkc.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-)
drivers/clk/meson/meson8b.h +1 -1
@@ -100,7 +100,7 @@#define CLKID_ASSIST_MISC 33#define CLKID_SPI 34#define CLKID_I2S_SPDIF 35 -#define CLKID_ETH 36 +/* #define CLKID_ETH */ #define CLKID_DEMUX 37#define CLKID_AIU_GLUE 38#define CLKID_IEC958 39
include/dt-bindings/clock/meson8b-clkc.h +1 -0
@@ -24,6 +24,7 @@#define CLKID_SAR_ADC 23#define CLKID_RNG0 25#define CLKID_SDIO 30 +#define CLKID_ETH 36#define CLKID_USB0 50#define CLKID_USB1 51#define CLKID_USB 55
Signature · 1 line
2.13.1
PATCH 5/13 clk: meson8b: export the ethernet gate clock
Quoted 27 lines · Martin Blumenstingl
Export the ethernet gate clock to the dt-bindings.
Signed-off-by Martin Blumenstingl <[email protected]>--- drivers/clk/meson/meson8b.h | 2 +- include/dt-bindings/clock/meson8b-clkc.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-)drivers/clk/meson/meson8b.h +1
-1@@ -100,7 +100,7 @@#define CLKID_ASSIST_MISC 33#define CLKID_SPI 34#define CLKID_I2S_SPDIF 35 -#define CLKID_ETH 36 +/* #define CLKID_ETH */ #define CLKID_DEMUX 37#define CLKID_AIU_GLUE 38#define CLKID_IEC958 39include/dt-bindings/clock/meson8b-clkc.h +0
-0
include/dt-bindings/clock/meson8b-clkc.h line 30
Quoted 7 lines
include/dt-bindings/clock/meson8b-clkc.h +1
-0@@ -24,6 +24,7 @@#define CLKID_SAR_ADC 23#define CLKID_RNG0 25#define CLKID_SDIO 30 +#define CLKID_ETH 36#define CLKID_USB0 50#define CLKID_USB1 51#define CLKID_USB 55
Martin Blumenstingl
reviewerPATCH 6/13 ARM: dts: meson8: add the PWM_E and PWM_F pins
In reply to Martin BlumenstinglThis adds the definition of the PWM_E (CBUS) and PWM_F (AOBUS) to meson8.dtsi, allowing devices to use them. PWM_E can be used on some devices to generate the 32.768kHz clock for the SDIO wifi module, while PWM_F can be used to control the power LED.
--- arch/arm/boot/dts/meson8.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+)
arch/arm/boot/dts/meson8.dtsi +14 -0
@@ -123,6 +123,13 @@ function = "remote"; }; }; + + pwm_f_ao_pins: pwm-f-ao { + mux { + groups = "pwm_f_ao"; + function = "pwm_f_ao"; + }; + }; }; };
@@ -168,6 +175,13 @@ function = "ethernet"; }; }; + + pwm_e_pins: pwm-e { + mux { + groups = "pwm_e"; + function = "pwm_e"; + }; + }; }; };
Signature · 1 line
2.13.1
PATCH 6/13 ARM: dts: meson8: add the PWM_E and PWM_F pins
Quoted 33 lines · Martin Blumenstingl
This adds the definition of the
PWM_E(CBUS) andPWM_F(AOBUS) tomeson8.dtsi, allowing devices to use them.PWM_Ecan be used on some devices to generate the 32.768kHz clock for the SDIO wifi module, whilePWM_Fcan be used to control the power LED.Signed-off-by Martin Blumenstingl <[email protected]>--- arch/arm/boot/dts/meson8.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+)arch/arm/boot/dts/meson8.dtsi +7
-0@@ -123,6 +123,13 @@ function = "remote"; }; }; + + pwm_f_ao_pins: pwm-f-ao { + mux { + groups = "pwm_f_ao"; + function = "pwm_f_ao"; + }; + }; }; };@@ -168,6 +175,13 @@ function = "ethernet"; }; };
arch/arm/boot/dts/meson8.dtsi line 187
Quoted 10 lines
arch/arm/boot/dts/meson8.dtsi +7
-0+ + pwm_e_pins: pwm-e { + mux { + groups = "pwm_e"; + function = "pwm_e"; + }; + }; }; };
Martin Blumenstingl
reviewerPATCH 7/13 ARM: dts: meson8: add the pins for the SDIO controller
In reply to Martin Blumenstingl--- arch/arm/boot/dts/meson8.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+)
arch/arm/boot/dts/meson8.dtsi +24 -0
@@ -158,6 +158,30 @@ gpio-ranges = <&pinctrl_cbus 0 0 120>; }; + sd_a_pins: sd-a { + mux { + groups = "sd_d0_a", "sd_d1_a", "sd_d2_a", + "sd_d3_a", "sd_clk_a", "sd_cmd_a"; + function = "sd_a"; + }; + }; + + sd_b_pins: sd-b { + mux { + groups = "sd_d0_b", "sd_d1_b", "sd_d2_b", + "sd_d3_b", "sd_clk_b", "sd_cmd_b"; + function = "sd_b"; + }; + }; + + sd_c_pins: sd-c { + mux { + groups = "sd_d0_c", "sd_d1_c", "sd_d2_c", + "sd_d3_c", "sd_clk_c", "sd_cmd_c"; + function = "sd_c"; + }; + }; + spi_nor_pins: nor { mux { groups = "nor_d", "nor_q", "nor_c", "nor_cs";
Signature · 1 line
2.13.1
PATCH 7/13 ARM: dts: meson8: add the pins for the SDIO controller
Quoted 31 lines · Martin Blumenstingl
Signed-off-by Martin Blumenstingl <[email protected]>--- arch/arm/boot/dts/meson8.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+)arch/arm/boot/dts/meson8.dtsi +17
-0@@ -158,6 +158,30 @@ gpio-ranges = <&pinctrl_cbus 0 0 120>; }; + sd_a_pins: sd-a { + mux { + groups = "sd_d0_a", "sd_d1_a", "sd_d2_a", + "sd_d3_a", "sd_clk_a", "sd_cmd_a"; + function = "sd_a"; + }; + }; + + sd_b_pins: sd-b { + mux { + groups = "sd_d0_b", "sd_d1_b", "sd_d2_b", + "sd_d3_b", "sd_clk_b", "sd_cmd_b"; + function = "sd_b"; + }; + }; + + sd_c_pins: sd-c {
arch/arm/boot/dts/meson8.dtsi line 187
Quoted 10 lines
arch/arm/boot/dts/meson8.dtsi +7
-0+ mux { + groups = "sd_d0_c", "sd_d1_c", "sd_d2_c", + "sd_d3_c", "sd_clk_c", "sd_cmd_c"; + function = "sd_c"; + }; + }; + spi_nor_pins: nor { mux { groups = "nor_d", "nor_q", "nor_c", "nor_cs";
Martin Blumenstingl
reviewerPATCH 8/13 ARM: dts: meson: add the SAR ADC
In reply to Martin BlumenstinglThis adds the SAR ADC to meson.dtsi and configures the clocks on Meson8 and Meson8b to allow boards to use it. Some boards use it to connect a button to it.
--- arch/arm/boot/dts/meson.dtsi | 8 ++++++++ arch/arm/boot/dts/meson8.dtsi | 8 ++++++++ arch/arm/boot/dts/meson8b.dtsi | 8 ++++++++ 3 files changed, 24 insertions(+)
arch/arm/boot/dts/meson.dtsi +8 -0
@@ -101,6 +101,14 @@ status = "disabled"; }; + saradc: adc at 8680 { + compatible = "amlogic,meson-saradc"; + reg = <0x8680 0x34>; + #io-channel-cells = <1>; + interrupts = <0 73 1>; + status = "disabled"; + }; + uart_C: serial at 8700 { compatible = "amlogic,meson-uart"; reg = <0x8700 0x18>;
arch/arm/boot/dts/meson8.dtsi +8 -0
@@ -232,6 +232,14 @@ arm,filter-ranges = <0x100000 0xc0000000>; }; +&saradc { + compatible = "amlogic,meson8-saradc", "amlogic,meson-saradc"; + clocks = <&clkc CLKID_XTAL>, + <&clkc CLKID_SAR_ADC>, + <&clkc CLKID_SANA>; + clock-names = "clkin", "core", "sana"; +}; + &spifc { clocks = <&clkc CLKID_CLK81>; };
arch/arm/boot/dts/meson8b.dtsi +8 -0
@@ -177,6 +177,14 @@ arm,filter-ranges = <0x100000 0xc0000000>; }; +&saradc { + compatible = "amlogic,meson8b-saradc", "amlogic,meson-saradc"; + clocks = <&clkc CLKID_XTAL>, + <&clkc CLKID_SAR_ADC>, + <&clkc CLKID_SANA>; + clock-names = "clkin", "core", "sana"; +}; + &uart_AO { clocks = <&clkc CLKID_CLK81>; };
Signature · 1 line
2.13.1
PATCH 8/13 ARM: dts: meson: add the SAR ADC
Quoted 16 lines · Martin Blumenstingl
This adds the SAR ADC to
meson.dtsiand configures the clocks on Meson8 and Meson8b to allow boards to use it. Some boards use it to connect a button to it.Signed-off-by Martin Blumenstingl <[email protected]>--- arch/arm/boot/dts/meson.dtsi | 8 ++++++++ arch/arm/boot/dts/meson8.dtsi | 8 ++++++++ arch/arm/boot/dts/meson8b.dtsi | 8 ++++++++ 3 files changed, 24 insertions(+)arch/arm/boot/dts/meson.dtsi +0
-0
arch/arm/boot/dts/meson.dtsi line 108
Quoted 8 lines
arch/arm/boot/dts/meson.dtsi +5
-0@@ -101,6 +101,14 @@ status = "disabled"; }; + saradc: adc at 8680 { + compatible = "amlogic,meson-saradc"; + reg = <0x8680 0x34>; + #io-channel-cells = <1>; + interrupts = <0 73 1>;
Can you use the correct GIC_ and IRQ_TYPE_ ... defines for the IRQ property ?
Quoted 35 lines
arch/arm/boot/dts/meson.dtsi +3
-0+ status = "disabled"; + }; + uart_C: serial at 8700 { compatible = "amlogic,meson-uart"; reg = <0x8700 0x18>;arch/arm/boot/dts/meson8.dtsi +8
-0@@ -232,6 +232,14 @@ arm,filter-ranges = <0x100000 0xc0000000>; }; +&saradc { + compatible = "amlogic,meson8-saradc", "amlogic,meson-saradc"; + clocks = <&clkc CLKID_XTAL>, + <&clkc CLKID_SAR_ADC>, + <&clkc CLKID_SANA>; + clock-names = "clkin", "core", "sana"; +}; + &spifc { clocks = <&clkc CLKID_CLK81>; };arch/arm/boot/dts/meson8b.dtsi +1
-0@@ -177,6 +177,14 @@ arm,filter-ranges = <0x100000 0xc0000000>; }; +&saradc {
arch/arm/boot/dts/meson8b.dtsi line 190
Quoted 10 lines
arch/arm/boot/dts/meson8b.dtsi +7
-0+ compatible = "amlogic,meson8b-saradc", "amlogic,meson-saradc"; + clocks = <&clkc CLKID_XTAL>, + <&clkc CLKID_SAR_ADC>, + <&clkc CLKID_SANA>; + clock-names = "clkin", "core", "sana"; +}; + &uart_AO { clocks = <&clkc CLKID_CLK81>; };
Apart from that :
Martin Blumenstingl
reviewerPATCH 9/13 ARM: dts: meson8: add reserved memory zones
In reply to Martin BlumenstinglThere seem to be two memory regions that need to be reserved, otherwise the system just hangs when running:
$ stress --vm-bytes $(awk '/MemFree/{printf "%d\n", $2 * 0.9;}' < /proc/meminfo)k \
--vm-keep -m 1The first memory region is really crucial and without it the system hangs. I could not find any references to this in Amlogic's GPL kernel sources.
The second region is used by the "suspend firmware". The u-boot sources (/arch/arm/cpu/aml_meson/m8/firmwareld.c) state that the suspend firmware is located at "64M + 15M" which matches CONFIG_MESON_SUSPEND in the Amlogic GPL kernel sources. The "suspend firmware" is responsible for waking up the system from suspend state.
This also fixes reading the full SD card as without this the system would simply hang (probably related to the first memory region, if some buffer is allocated there).
--- arch/arm/boot/dts/meson8.dtsi | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+)
arch/arm/boot/dts/meson8.dtsi +27 -0
@@ -83,6 +83,33 @@ reg = <0x203>; }; }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* 2 MiB reserved for Hardware ROM Firmware? */ + hwrom_reserved: hwrom at 0 { + reg = <0x0 0x200000>; + no-map; + }; + + /* + * 1 MiB reserved for the "ARM Power Firmware": this is ARM + * code which is responsible for system suspend. It loads a + * piece of ARC code ("arc_power" in the vendor u-boot tree) + * into SRAM, executes that and shuts down the (last) ARM core. + * The arc_power firmware then checks various wakeup sources + * (IR remote receiver, HDMI CEC, WIFI and Bluetooth wakeup or + * simply the power key) and re-starts the ARM core once it + * detects a wakeup request. + */ + suspend_firmware: secmon at 4f00000 { + reg = <0x4f00000 0x100000>; + no-map; + }; + }; }; /* end of / */ &aobus {
Signature · 1 line
2.13.1
PATCH 9/13 ARM: dts: meson8: add reserved memory zones
Quoted 52 lines · Martin Blumenstingl
There seem to be two memory regions that need to be reserved, otherwise the system just hangs when running:
$ stress --vm-bytes $(awk '/MemFree/{printf "%d\n", $2 * 0.9;}' < /proc/meminfo)k \ --vm-keep -m 1The first memory region is really crucial and without it the system hangs. I could not find any references to this in Amlogic's GPL kernel sources.
The second region is used by the "suspend firmware". The u-boot sources (/arch/arm/cpu/aml_meson/m8/firmwareld.c) state that the suspend firmware is located at "64M + 15M" which matchesCONFIG_MESON_SUSPENDin the Amlogic GPL kernel sources. The "suspend firmware" is responsible for waking up the system from suspend state.This also fixes reading the full SD card as without this the system would simply hang (probably related to the first memory region, if some buffer is allocated there).
Signed-off-by Martin Blumenstingl <[email protected]>--- arch/arm/boot/dts/meson8.dtsi | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+)arch/arm/boot/dts/meson8.dtsi +20
-0@@ -83,6 +83,33 @@ reg = <0x203>; }; }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* 2 MiB reserved for Hardware ROM Firmware? */ + hwrom_reserved: hwrom at 0 { + reg = <0x0 0x200000>; + no-map; + }; + + /* + * 1 MiB reserved for the "ARM Power Firmware": this is ARM + * code which is responsible for system suspend. It loads a + * piece of ARC code ("arc_power" in the vendor u-boot tree) + * into SRAM, executes that and shuts down the (last) ARM core. + * The arc_power firmware then checks various wakeup sources + * (IR remote receiver, HDMI CEC, WIFI and Bluetooth wakeup or + * simply the power key) and re-starts the ARM core once it
arch/arm/boot/dts/meson8.dtsi line 115
Quoted 10 lines
arch/arm/boot/dts/meson8.dtsi +7
-0+ * detects a wakeup request. + */ + suspend_firmware: secmon at 4f00000 { + reg = <0x4f00000 0x100000>; + no-map; + }; + }; }; /* end of / */ &aobus {
Good, but maybe you could add _reserved to the secmon alias.
Apart of that :
Martin Blumenstingl
reviewerPATCH 9/13 ARM: dts: meson8: add reserved memory zones
Quoted 61 lines · Neil Armstrong
Quoted 60 lines · Martin Blumenstingl
There seem to be two memory regions that need to be reserved, otherwise the system just hangs when running:
$ stress --vm-bytes $(awk '/MemFree/{printf "%d\n", $2 * 0.9;}' < /proc/meminfo)k \ --vm-keep -m 1The first memory region is really crucial and without it the system hangs. I could not find any references to this in Amlogic's GPL kernel sources.
The second region is used by the "suspend firmware". The u-boot sources (/arch/arm/cpu/aml_meson/m8/firmwareld.c) state that the suspend firmware is located at "64M + 15M" which matchesCONFIG_MESON_SUSPENDin the Amlogic GPL kernel sources. The "suspend firmware" is responsible for waking up the system from suspend state.This also fixes reading the full SD card as without this the system would simply hang (probably related to the first memory region, if some buffer is allocated there).
Signed-off-by Martin Blumenstingl <[email protected]>--- arch/arm/boot/dts/meson8.dtsi | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+)arch/arm/boot/dts/meson8.dtsi +27
-0@@ -83,6 +83,33 @@ reg = <0x203>; }; }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* 2 MiB reserved for Hardware ROM Firmware? */ + hwrom_reserved: hwrom at 0 { + reg = <0x0 0x200000>; + no-map; + }; + + /* + * 1 MiB reserved for the "ARM Power Firmware": this is ARM + * code which is responsible for system suspend. It loads a + * piece of ARC code ("arc_power" in the vendor u-boot tree) + * into SRAM, executes that and shuts down the (last) ARM core. + * The arc_power firmware then checks various wakeup sources + * (IR remote receiver, HDMI CEC, WIFI and Bluetooth wakeup or + * simply the power key) and re-starts the ARM core once it + * detects a wakeup request. + */ + suspend_firmware: secmon at 4f00000 { + reg = <0x4f00000 0x100000>; + no-map; + }; + }; }; /* end of / */
Quoted 4 lines
arch/arm/boot/dts/meson8.dtsi line 115
Quoted 2 lines
arch/arm/boot/dts/meson8.dtsi +0
-0&aobus {Good, but maybe you could add
_reservedto the secmon alias.
good catch, thanks
it seems that "secmon@" is still a copy-and-paste left-over so I'd rather change the whole line to "power_firmware:
power-firmware-memory at 4f00000" (as it's definitely not the secure monitor firmware) instead
does that also sound good for you?
Regards,
Martin
Martin Blumenstingl
reviewerPATCH 10/13 ARM: dts: meson: add the hardware random number generator
In reply to Martin BlumenstinglAll supported Meson SoCs have a random number generator in CBUS. Newer SoCs (GXBB, GXL and GXM) provide only one 32-bit random number register, whereas the older SoCs (Meson6, Meson8 and Meson8b) have two 32-bit random number registers. The existing meson-rng driver only supports the lower 32-bit - but it still works fine on the older SoCs apart from this small limitation.
--- arch/arm/boot/dts/meson.dtsi | 5 +++++ arch/arm/boot/dts/meson8.dtsi | 5 +++++ arch/arm/boot/dts/meson8b.dtsi | 5 +++++ 3 files changed, 15 insertions(+)
arch/arm/boot/dts/meson.dtsi +5 -0
@@ -78,6 +78,11 @@ #size-cells = <1>; ranges = <0x0 0xc1100000 0x200000>; + hwrng: rng at 8100 { + compatible = "amlogic,meson-rng"; + reg = <0x8100 0x8>; + }; + uart_A: serial at 84c0 { compatible = "amlogic,meson-uart"; reg = <0x84c0 0x18>;
arch/arm/boot/dts/meson8.dtsi +5 -0
@@ -241,6 +241,11 @@ clock-names = "stmmaceth"; }; +&hwrng { + clocks = <&clkc CLKID_RNG0>; + clock-names = "core"; +}; + &i2c_AO { clocks = <&clkc CLKID_CLK81>; };
arch/arm/boot/dts/meson8b.dtsi +5 -0
@@ -171,6 +171,11 @@ }; }; +&hwrng { + clocks = <&clkc CLKID_RNG0>; + clock-names = "core"; +}; + &L2 { arm,data-latency = <3 3 3>; arm,tag-latency = <2 2 2>;
Signature · 1 line
2.13.1
PATCH 10/13 ARM: dts: meson: add the hardware random number generator
Quoted 19 lines · Martin Blumenstingl
All supported Meson SoCs have a random number generator in CBUS. Newer SoCs (GXBB, GXL and GXM) provide only one 32-bit random number register, whereas the older SoCs (Meson6, Meson8 and Meson8b) have two 32-bit random number registers. The existing meson-rng driver only supports the lower 32-bit - but it still works fine on the older SoCs apart from this small limitation.
Signed-off-by Martin Blumenstingl <[email protected]>--- arch/arm/boot/dts/meson.dtsi | 5 +++++ arch/arm/boot/dts/meson8.dtsi | 5 +++++ arch/arm/boot/dts/meson8b.dtsi | 5 +++++ 3 files changed, 15 insertions(+)arch/arm/boot/dts/meson.dtsi +0
-0
arch/arm/boot/dts/meson.dtsi line 85
Quoted 8 lines
arch/arm/boot/dts/meson.dtsi +5
-0@@ -78,6 +78,11 @@ #size-cells = <1>; ranges = <0x0 0xc1100000 0x200000>; + hwrng: rng at 8100 { + compatible = "amlogic,meson-rng"; + reg = <0x8100 0x8>; + }; +
Maybe you can add a "amlogic,mesonX-rng" before the "amlogic,meson-rng" here so you will be able to support the different register layout and put the correct number in the meson8 and meson8b dtsi files.
Quoted 26 lines
arch/arm/boot/dts/meson.dtsi +0
-0uart_A: serial at 84c0 { compatible = "amlogic,meson-uart"; reg = <0x84c0 0x18>;arch/arm/boot/dts/meson8.dtsi +5
-0@@ -241,6 +241,11 @@ clock-names = "stmmaceth"; }; +&hwrng { + clocks = <&clkc CLKID_RNG0>; + clock-names = "core"; +}; + &i2c_AO { clocks = <&clkc CLKID_CLK81>; };arch/arm/boot/dts/meson8b.dtsi +0
-0@@ -171,6 +171,11 @@ };
arch/arm/boot/dts/meson8b.dtsi line 181
Quoted 10 lines
arch/arm/boot/dts/meson8b.dtsi +5
-0}; +&hwrng { + clocks = <&clkc CLKID_RNG0>; + clock-names = "core"; +}; + &L2 { arm,data-latency = <3 3 3>; arm,tag-latency = <2 2 2>;
Apart from that :
Martin Blumenstingl
reviewerPATCH 11/13 ARM: dts: meson: add USB support on Meson8 and Meson8b
In reply to Martin BlumenstinglThis adds the DWC2 USB controller nodes and the corresponding USB2 PHY nodes to meson.dtsi (as the same - or at least a very similar) IP block is used on all SoCs (at the same physical address). Additionally meson8.dtsi and meson8b.dtsi add the required clocks to the DWC2 and USB2 PHY nodes, otherwise the DWC2 controller cannot be initialized by the dwc2 driver.
--- arch/arm/boot/dts/meson.dtsi | 38 ++++++++++++++++++++++++++++++++++++++ arch/arm/boot/dts/meson8.dtsi | 24 ++++++++++++++++++++++++ arch/arm/boot/dts/meson8b.dtsi | 26 ++++++++++++++++++++++++++ 3 files changed, 88 insertions(+)
arch/arm/boot/dts/meson.dtsi +38 -0
@@ -130,6 +130,20 @@ status = "disabled"; }; + usb0_phy: phy at 8800 { + compatible = "amlogic,meson-mx-usb2-phy"; + #phy-cells = <0>; + reg = <0x8800 0x20>; + status = "disabled"; + }; + + usb1_phy: phy at 8820 { + compatible = "amlogic,meson-mx-usb2-phy"; + #phy-cells = <0>; + reg = <0x8820 0x20>; + status = "disabled"; + }; + spifc: spi at 8c80 { compatible = "amlogic,meson6-spifc"; reg = <0x8c80 0x80>;
@@ -182,6 +196,30 @@ }; }; + usb0: usb at c9040000 { + compatible = "snps,dwc2"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xc9040000 0x40000>; + interrupts = <0 30 1>; + phys = <&usb0_phy>; + phy-names = "usb2-phy"; + dr_mode = "host"; + status = "disabled"; + }; + + usb1: usb at c90c0000 { + compatible = "snps,dwc2"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xc90c0000 0x40000>; + interrupts = <0 31 1>; + phys = <&usb1_phy>; + phy-names = "usb2-phy"; + dr_mode = "host"; + status = "disabled"; + }; + ethmac: ethernet at c9410000 { compatible = "amlogic,meson6-dwmac", "snps,dwmac"; reg = <0xc9410000 0x10000
arch/arm/boot/dts/meson8.dtsi +24 -0
@@ -291,3 +291,27 @@ &uart_C { clocks = <&clkc CLKID_CLK81>; }; + +&usb0 { + compatible = "amlogic,meson8-usb", "snps,dwc2"; + clocks = <&clkc CLKID_USB0_DDR_BRIDGE>; + clock-names = "otg"; +}; + +&usb1 { + compatible = "amlogic,meson8-usb", "snps,dwc2"; + clocks = <&clkc CLKID_USB1_DDR_BRIDGE>; + clock-names = "otg"; +}; + +&usb0_phy { + compatible = "amlogic,meson8-usb2-phy", "amlogic,meson-mx-usb2-phy"; + clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>; + clock-names = "usb_general", "usb"; +}; + +&usb1_phy { + compatible = "amlogic,meson8-usb2-phy", "amlogic,meson-mx-usb2-phy"; + clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>; + clock-names = "usb_general", "usb"; +};
arch/arm/boot/dts/meson8b.dtsi +26 -0
@@ -205,3 +205,29 @@ &uart_C { clocks = <&clkc CLKID_CLK81>; }; + +&usb0 { + compatible = "amlogic,meson8b-usb", "snps,dwc2"; + clocks = <&clkc CLKID_USB0_DDR_BRIDGE>; + clock-names = "otg"; +}; + +&usb1 { + compatible = "amlogic,meson8b-usb", "snps,dwc2"; + clocks = <&clkc CLKID_USB1_DDR_BRIDGE>; + clock-names = "otg"; +}; + +&usb0_phy { + compatible = "amlogic,meson8b-usb2-phy", "amlogic,meson-mx-usb2-phy"; + clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>; + clock-names = "usb_general", "usb"; + resets = <&reset RESET_USB_OTG>; +}; + +&usb1_phy { + compatible = "amlogic,meson8b-usb2-phy", "amlogic,meson-mx-usb2-phy"; + clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>; + clock-names = "usb_general", "usb"; + resets = <&reset RESET_USB_OTG>; +};
Signature · 1 line
2.13.1
PATCH 11/13 ARM: dts: meson: add USB support on Meson8 and Meson8b
Quoted 40 lines · Martin Blumenstingl
This adds the DWC2 USB controller nodes and the corresponding USB2 PHY nodes to
meson.dtsi(as the same - or at least a very similar) IP block is used on all SoCs (at the same physical address). Additionallymeson8.dtsiandmeson8b.dtsiadd the required clocks to the DWC2 and USB2 PHY nodes, otherwise the DWC2 controller cannot be initialized by the dwc2 driver.Signed-off-by Martin Blumenstingl <[email protected]>--- arch/arm/boot/dts/meson.dtsi | 38 ++++++++++++++++++++++++++++++++++++++ arch/arm/boot/dts/meson8.dtsi | 24 ++++++++++++++++++++++++ arch/arm/boot/dts/meson8b.dtsi | 26 ++++++++++++++++++++++++++ 3 files changed, 88 insertions(+)arch/arm/boot/dts/meson.dtsi +14
-0@@ -130,6 +130,20 @@ status = "disabled"; }; + usb0_phy: phy at 8800 { + compatible = "amlogic,meson-mx-usb2-phy"; + #phy-cells = <0>; + reg = <0x8800 0x20>; + status = "disabled"; + }; + + usb1_phy: phy at 8820 { + compatible = "amlogic,meson-mx-usb2-phy"; + #phy-cells = <0>; + reg = <0x8820 0x20>; + status = "disabled"; + }; + spifc: spi at 8c80 { compatible = "amlogic,meson6-spifc"; reg = <0x8c80 0x80>;
arch/arm/boot/dts/meson.dtsi line 204
Quoted 9 lines
arch/arm/boot/dts/meson.dtsi +6
-0@@ -182,6 +196,30 @@ }; }; + usb0: usb at c9040000 { + compatible = "snps,dwc2"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xc9040000 0x40000>; + interrupts = <0 30 1>;
Same as patch 8
arch/arm/boot/dts/meson.dtsi line 216
Quoted 12 lines
arch/arm/boot/dts/meson.dtsi +12
-0+ phys = <&usb0_phy>; + phy-names = "usb2-phy"; + dr_mode = "host"; + status = "disabled"; + }; + + usb1: usb at c90c0000 { + compatible = "snps,dwc2"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xc90c0000 0x40000>; + interrupts = <0 31 1>;
Same as patch 8
Quoted 66 lines
arch/arm/boot/dts/meson.dtsi +6
-0+ phys = <&usb1_phy>; + phy-names = "usb2-phy"; + dr_mode = "host"; + status = "disabled"; + }; + ethmac: ethernet at c9410000 { compatible = "amlogic,meson6-dwmac", "snps,dwmac"; reg = <0xc9410000 0x10000arch/arm/boot/dts/meson8.dtsi +24
-0@@ -291,3 +291,27 @@ &uart_C { clocks = <&clkc CLKID_CLK81>; }; + +&usb0 { + compatible = "amlogic,meson8-usb", "snps,dwc2"; + clocks = <&clkc CLKID_USB0_DDR_BRIDGE>; + clock-names = "otg"; +}; + +&usb1 { + compatible = "amlogic,meson8-usb", "snps,dwc2"; + clocks = <&clkc CLKID_USB1_DDR_BRIDGE>; + clock-names = "otg"; +}; + +&usb0_phy { + compatible = "amlogic,meson8-usb2-phy", "amlogic,meson-mx-usb2-phy"; + clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>; + clock-names = "usb_general", "usb"; +}; + +&usb1_phy { + compatible = "amlogic,meson8-usb2-phy", "amlogic,meson-mx-usb2-phy"; + clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>; + clock-names = "usb_general", "usb"; +};arch/arm/boot/dts/meson8b.dtsi +16
-0@@ -205,3 +205,29 @@ &uart_C { clocks = <&clkc CLKID_CLK81>; }; + +&usb0 { + compatible = "amlogic,meson8b-usb", "snps,dwc2"; + clocks = <&clkc CLKID_USB0_DDR_BRIDGE>; + clock-names = "otg"; +}; + +&usb1 { + compatible = "amlogic,meson8b-usb", "snps,dwc2"; + clocks = <&clkc CLKID_USB1_DDR_BRIDGE>; + clock-names = "otg"; +}; + +&usb0_phy { + compatible = "amlogic,meson8b-usb2-phy", "amlogic,meson-mx-usb2-phy"; + clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
arch/arm/boot/dts/meson8b.dtsi line 233
Quoted 10 lines
arch/arm/boot/dts/meson8b.dtsi +10
-0+ clock-names = "usb_general", "usb"; + resets = <&reset RESET_USB_OTG>; +}; + +&usb1_phy { + compatible = "amlogic,meson8b-usb2-phy", "amlogic,meson-mx-usb2-phy"; + clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>; + clock-names = "usb_general", "usb"; + resets = <&reset RESET_USB_OTG>; +};
Apart from that :
Martin Blumenstingl
reviewerPATCH 12/13 ARM: dts: meson8b: add the SCU device node
In reply to Martin BlumenstinglAmlogic's Meson8b SoC has a Snoop Control Unit (SCU), just like many other Cortex-A5 SoCs. Add the corresponding devicetree node so it can be used during SMP boot.
--- arch/arm/boot/dts/meson8.dtsi | 5 +++++ arch/arm/boot/dts/meson8b.dtsi | 5 +++++ 2 files changed, 10 insertions(+)
arch/arm/boot/dts/meson8.dtsi +5 -0
@@ -110,6 +110,11 @@ no-map; }; }; + + scu at c4300000 { + compatible = "arm,cortex-a9-scu"; + reg = <0xc4300000 0x100>; + }; }; /* end of / */ &aobus {
arch/arm/boot/dts/meson8b.dtsi +5 -0
@@ -82,6 +82,11 @@ reg = <0x203>; }; }; + + scu at c4300000 { + compatible = "arm,cortex-a5-scu"; + reg = <0xc4300000 0x100>; + }; }; /* end of / */ &aobus {
Signature · 1 line
2.13.1
PATCH 12/13 ARM: dts: meson8b: add the SCU device node
Quoted 33 lines · Martin Blumenstingl
Amlogic's Meson8b SoC has a Snoop Control Unit (SCU), just like many other Cortex-A5 SoCs. Add the corresponding devicetree node so it can be used during SMP boot.
Signed-off-by Martin Blumenstingl <[email protected]>--- arch/arm/boot/dts/meson8.dtsi | 5 +++++ arch/arm/boot/dts/meson8b.dtsi | 5 +++++ 2 files changed, 10 insertions(+)arch/arm/boot/dts/meson8.dtsi +5
-0@@ -110,6 +110,11 @@ no-map; }; }; + + scu at c4300000 { + compatible = "arm,cortex-a9-scu"; + reg = <0xc4300000 0x100>; + }; }; /* end of / */ &aobus {arch/arm/boot/dts/meson8b.dtsi +0
-0@@ -82,6 +82,11 @@ reg = <0x203>;
arch/arm/boot/dts/meson8b.dtsi line 92
Quoted 10 lines
arch/arm/boot/dts/meson8b.dtsi +5
-0}; }; + + scu at c4300000 { + compatible = "arm,cortex-a5-scu"; + reg = <0xc4300000 0x100>; + }; }; /* end of / */ &aobus {
Martin Blumenstingl
reviewerPATCH 13/13 ARM: dts: meson: use the real ethernet clock on Meson8 and Meson8b
In reply to Martin BlumenstinglUntil now clk81 was used as gate clock for the ethernet controller on Meson8 whereas Meson8b did not configure a gate clock at all. Use CLKID_ETH for both SoCs, which is the real gate clock for the ethernet controller.
--- arch/arm/boot/dts/meson8.dtsi | 2 +- arch/arm/boot/dts/meson8b.dtsi | 5 +++++ 2 files changed, 6 insertions(+), 1 deletion(-)
arch/arm/boot/dts/meson8.dtsi +1 -1
@@ -242,7 +242,7 @@ }; ðmac { - clocks = <&clkc CLKID_CLK81>; + clocks = <&clkc CLKID_ETH>; clock-names = "stmmaceth"; };
arch/arm/boot/dts/meson8b.dtsi +5 -0
@@ -176,6 +176,11 @@ }; }; +ðmac { + clocks = <&clkc CLKID_ETH>; + clock-names = "stmmaceth"; +}; + &hwrng { clocks = <&clkc CLKID_RNG0>; clock-names = "core";
Signature · 1 line
2.13.1
PATCH 13/13 ARM: dts: meson: use the real ethernet clock on Meson8 and Meson8b
Quoted 31 lines · Martin Blumenstingl
Until now clk81 was used as gate clock for the ethernet controller on Meson8 whereas Meson8b did not configure a gate clock at all. Use
CLKID_ETHfor both SoCs, which is the real gate clock for the ethernet controller.Signed-off-by Martin Blumenstingl <[email protected]>--- arch/arm/boot/dts/meson8.dtsi | 2 +- arch/arm/boot/dts/meson8b.dtsi | 5 +++++ 2 files changed, 6 insertions(+), 1 deletion(-)arch/arm/boot/dts/meson8.dtsi +1
-1@@ -242,7 +242,7 @@ }; ðmac { - clocks = <&clkc CLKID_CLK81>; + clocks = <&clkc CLKID_ETH>; clock-names = "stmmaceth"; };arch/arm/boot/dts/meson8b.dtsi +0
-0@@ -176,6 +176,11 @@ };
arch/arm/boot/dts/meson8b.dtsi line 186
Quoted 10 lines
arch/arm/boot/dts/meson8b.dtsi +5
-0}; +ðmac { + clocks = <&clkc CLKID_ETH>; + clock-names = "stmmaceth"; +}; + &hwrng { clocks = <&clkc CLKID_RNG0>; clock-names = "core";
cover add support for more devices on Meson8 and Meson8b
In reply to Martin BlumenstinglQuoted 30 lines · Martin Blumenstingl
This series adds:
- USB support on Meson8 and Meson8b (it seems that some boards show an ? error when trying to initialize one of the USB2 PHYs, but we have the ? same problem on some GXBB boards. it is working fine for me - on a board ? which is not supported upstream yet)
- hardware random number generator support (Meson8 and Meson8b seem to ? have two 32-bit hardware random number generator registers, while the ? GX SoCs only have one. This is not handled by the meson-rng driver yet, ? but that can still be improved later on)
- SAR ADC support
- add reserved memory zones to fix random hangs when filling the memory ? (currently only on Meson8 until I have a Meson8b device to test if the ? same problem appears there as well)
- use the real ethernet clock on Meson8 and Meson8b to fix ethernet when ? the bootloader does not enable the gate clock
- add the SCU (Snoop Control Unit) which is needed for SMP support
- minor preparations for further .dts updates as this already exports the ? SDIO clocks (a driver for this MMC controller is work-in-progress) as ? well as the corresponding pin definitions inmeson8.dtsi
- this adds thepwm_e(typically used for the 32.768 kHz LPO clock for the ? SDIO wifi chip) andpwm_f(used on some boards for the dimmable power ? LED) pins tomeson8.dtsiNOTE: the .dts changes from this series depend on my previous patch from [0]: "ARM: dts: meson8: fix the IR receiver pins"
[0] http://lists.infradead.org/pipermail/linux-amlogic/2017-June/003983.html
Quoted 6 lines
Martin Blumenstingl (13):
? clk: meson8b: export the SAR ADC clocks
? clk: meson8b: export the SDIO clock
? clk: meson8b: export the gate clock for the HW random number generator ? clk: meson8b: export the USB clocks
? clk: meson8b: export the ethernet gate clock
Applied these 5 clk patches to next/headers with Neil's Acks.
Quoted 17 lines
? ARM: dts: meson8: add the
PWM_EandPWM_Fpins
? ARM: dts: meson8: add the pins for the SDIO controller ? ARM: dts: meson: add the SAR ADC
? ARM: dts: meson8: add reserved memory zones
? ARM: dts: meson: add the hardware random number generator ? ARM: dts: meson: add USB support on Meson8 and Meson8b ? ARM: dts: meson8b: add the SCU device node
? ARM: dts: meson: use the real ethernet clock on Meson8 and Meson8b?arch/arm/boot/dts/meson.dtsi?????????????|??51 +++++++++++++++ ?arch/arm/boot/dts/meson8.dtsi????????????| 109
++++++++++++++++++++++++++++++-?arch/arm/boot/dts/meson8b.dtsi???????????|??49 ++++++++++++++ ?drivers/clk/meson/meson8b.h??????????????|??20 +++--- ?include/dt-bindings/clock/meson8b-clkc.h |??10 +++?5 files changed, 228 insertions(+), 11 deletions(-)
Martin Blumenstingl
reviewercover add support for more devices on Meson8 and Meson8b
Hi Jerome,
Quoted 31 lines · Jerome Brunet
Quoted 30 lines · Martin Blumenstingl
This series adds:
- USB support on Meson8 and Meson8b (it seems that some boards show an error when trying to initialize one of the USB2 PHYs, but we have the same problem on some GXBB boards. it is working fine for me - on a board which is not supported upstream yet)
- hardware random number generator support (Meson8 and Meson8b seem to have two 32-bit hardware random number generator registers, while the GX SoCs only have one. This is not handled by the meson-rng driver yet, but that can still be improved later on)
- SAR ADC support
- add reserved memory zones to fix random hangs when filling the memory (currently only on Meson8 until I have a Meson8b device to test if the same problem appears there as well)
- use the real ethernet clock on Meson8 and Meson8b to fix ethernet when the bootloader does not enable the gate clock
- add the SCU (Snoop Control Unit) which is needed for SMP support
- minor preparations for further .dts updates as this already exports the SDIO clocks (a driver for this MMC controller is work-in-progress) as well as the corresponding pin definitions inmeson8.dtsi
- this adds thepwm_e(typically used for the 32.768 kHz LPO clock for the SDIO wifi chip) andpwm_f(used on some boards for the dimmable power LED) pins tomeson8.dtsiNOTE: the .dts changes from this series depend on my previous patch from [0]: "ARM: dts: meson8: fix the IR receiver pins"
[0] http://lists.infradead.org/pipermail/linux-amlogic/2017-June/003983.html
Quoted 8 lines
Quoted 6 lines
Martin Blumenstingl (13):
clk: meson8b: export the SAR ADC clocks
clk: meson8b: export the SDIO clock
clk: meson8b: export the gate clock for the HW random number generator
clk: meson8b: export the USB clocks
clk: meson8b: export the ethernet gate clockApplied these 5 clk patches to next/headers with Neil's Acks.
thank you!
Quoted 8 lines
Quoted 8 lines
ARM: dts: meson8: add the
PWM_EandPWM_Fpins
ARM: dts: meson8: add the pins for the SDIO controller
ARM: dts: meson: add the SAR ADC
ARM: dts: meson8: add reserved memory zones
ARM: dts: meson: add the hardware random number generator
ARM: dts: meson: add USB support on Meson8 and Meson8b
ARM: dts: meson8b: add the SCU device node
ARM: dts: meson: use the real ethernet clock on Meson8 and Meson8b
I will send a v2 (which will address Neil's comments on these) soon
Quoted 9 lines
Quoted 8 lines
arch/arm/boot/dts/meson.dtsi | 51 +++++++++++++++ arch/arm/boot/dts/meson8.dtsi | 109 ++++++++++++++++++++++++++++++- arch/arm/boot/dts/meson8b.dtsi | 49 ++++++++++++++ drivers/clk/meson/meson8b.h | 20 +++--- include/dt-bindings/clock/meson8b-clkc.h | 10 +++ 5 files changed, 228 insertions(+), 11 deletions(-)
Martin Blumenstingl
reviewerv2 cover add support for more devices on Meson8 and Meson8b
In reply to Martin BlumenstinglThis series adds:
- USB support on Meson8 and Meson8b (it seems that some boards show an error when trying to initialize one of the USB2 PHYs, but we have the same problem on some GXBB boards. it is working fine for me - on a board which is not supported upstream yet)
- hardware random number generator support (Meson8 and Meson8b seem to have two 32-bit hardware random number generator registers, while the GX SoCs only have one. This is not handled by the meson-rng driver yet, but that can still be improved later on)
- SAR ADC support
- add reserved memory zones to fix random hangs when filling the memory (currently only on Meson8 until I have a Meson8b device to test if the same problem appears there as well)
- use the real ethernet clock on Meson8 and Meson8b to fix ethernet when the bootloader does not enable the gate clock
- add the SCU (Snoop Control Unit) which is needed for SMP support
- minor preparations for further .dts updates as this already exports the SDIO clocks (a driver for this MMC controller is work-in-progress) as well as the corresponding pin definitions in meson8.dtsi
- this adds the pwm_e (typically used for the 32.768 kHz LPO clock for the SDIO wifi chip) and pwm_f (used on some boards for the dimmable power LED) pins to meson8.dtsi
NOTE: the .dts changes from this series depend on my previous patch from [0]: "ARM: dts: meson8: fix the IR receiver pins"
[0] http://lists.infradead.org/pipermail/linux-amlogic/2017-June/003983.html
Changes since v1:
- dropped patches 1-5 which export various clock IDs as these are already applied by Jerome to clk-meson's next/headers branch
- added new patch "ARM: dts: meson: use C preprocessor friendly include syntax" so we can use preprocessor macros like GIC_SPI and IRQ_TYPE_EDGE_RISING in the SAR ADC and USB patches
- added new patch "ARM: dts: meson: use GIC_SPI and IRQ_TYPE_EDGE_RISING macros" so the GIC_SPI and IRQ_TYPE_EDGE_RISING preprocessor macros are available for the SAR ADC and USB patches (as a side-effect this also provides a nice cleanup)
- use GIC_SPI and IRQ_TYPE_EDGE_RISING instead of magic numbers in patch "ARM: dts: meson: add the SAR ADC" and "ARM: dts: meson: add USB support on Meson8 and Meson8b"
- added (currently unused) "amlogic,meson8-rng" and "amlogic,meson8b-rng" compatibles in "ARM: dts: meson: add the hardware random number generator"
- fixed node name (it's the memory region of the ARM Power Firmware, not the secure monitor firmware) and dropped node alias (of both reserved memory zones) in "ARM: dts: meson8: add reserved memory zones"
- added Neil's Reviewed-By
Martin Blumenstingl (10):
ARM: dts: meson: use C preprocessor friendly include syntax
ARM: dts: meson: use GIC_SPI and IRQ_TYPE_EDGE_RISING macros
ARM: dts: meson8: add the PWM_E and PWM_F pins
ARM: dts: meson8: add the pins for the SDIO controller
ARM: dts: meson: add the SAR ADC
ARM: dts: meson8: add reserved memory zones
ARM: dts: meson: add the hardware random number generator
ARM: dts: meson: add USB support on Meson8 and Meson8b
ARM: dts: meson8b: add the SCU device node
ARM: dts: meson: use the real ethernet clock on Meson8 and Meson8b
arch/arm/boot/dts/meson.dtsi | 75 +++++++++++++++++++---- arch/arm/boot/dts/meson6-atv1200.dts | 2 +- arch/arm/boot/dts/meson6.dtsi | 2 +- arch/arm/boot/dts/meson8.dtsi | 112 ++++++++++++++++++++++++++++++++++- arch/arm/boot/dts/meson8b.dtsi | 50 ++++++++++++++++ 5 files changed, 226 insertions(+), 15 deletions(-)
Signature · 1 line
2.13.1
Martin Blumenstingl
reviewerPATCH v2 1/10 ARM: dts: meson: use C preprocessor friendly include syntax
This replaces the "/include/" syntax with the "#include" syntax in all Amlogic Meson .dts and .dtsi files. That is required to use preprocessor defines (like GIC_SPI and IRQ_TYPE_EDGE_RISING) in meson.dtsi (all files which directly or indirectly include meson.dtsi need to use the "#include" syntax, otherwise the .dts files cannot be compiled).
--- arch/arm/boot/dts/meson6-atv1200.dts | 2 +- arch/arm/boot/dts/meson6.dtsi | 2 +- arch/arm/boot/dts/meson8.dtsi | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-)
arch/arm/boot/dts/meson6-atv1200.dts +1 -1
@@ -46,7 +46,7 @@ */ /dts-v1/; -/include/ "meson6.dtsi" +#include "meson6.dtsi" / { model = "Geniatech ATV1200";
arch/arm/boot/dts/meson6.dtsi +1 -1
@@ -45,7 +45,7 @@ * OTHER DEALINGS IN THE SOFTWARE. */ -/include/ "meson.dtsi" +#include "meson.dtsi" / { model = "Amlogic Meson6 SoC";
arch/arm/boot/dts/meson8.dtsi +1 -1
@@ -45,7 +45,7 @@ #include <dt-bindings/clock/meson8b-clkc.h> #include <dt-bindings/gpio/meson8-gpio.h> -/include/ "meson.dtsi" +#include "meson.dtsi" / { model = "Amlogic Meson8 SoC";
Signature · 1 line
2.13.1
Martin Blumenstingl
reviewerPATCH v2 2/10 ARM: dts: meson: use GIC_SPI and IRQ_TYPE_EDGE_RISING macros
In reply to Martin BlumenstinglThis makes meson.dtsi easier to read as we are not using magic numbers for the GIC interrupt type (GIC_SPI) and the interrupt polarity (IRQ_TYPE_EDGE_RISING).
--- arch/arm/boot/dts/meson.dtsi | 24 +++++++++++++----------- 1 file changed, 13 insertions(+), 11 deletions(-)
arch/arm/boot/dts/meson.dtsi +13 -11
@@ -45,6 +45,8 @@ * OTHER DEALINGS IN THE SOFTWARE. */ +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> /include/ "skeleton.dtsi" / {
@@ -81,21 +83,21 @@ uart_A: serial at 84c0 { compatible = "amlogic,meson-uart"; reg = <0x84c0 0x18>; - interrupts = <0 26 1>; + interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>; status = "disabled"; }; uart_B: serial at 84dc { compatible = "amlogic,meson-uart"; reg = <0x84dc 0x18>; - interrupts = <0 75 1>; + interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>; status = "disabled"; }; i2c_A: i2c at 8500 { compatible = "amlogic,meson6-i2c"; reg = <0x8500 0x20>; - interrupts = <0 21 1>; + interrupts = <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>; #address-cells = <1>; #size-cells = <0>; status = "disabled";
@@ -104,14 +106,14 @@ uart_C: serial at 8700 { compatible = "amlogic,meson-uart"; reg = <0x8700 0x18>; - interrupts = <0 93 1>; + interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>; status = "disabled"; }; i2c_B: i2c at 87c0 { compatible = "amlogic,meson6-i2c"; reg = <0x87c0 0x20>; - interrupts = <0 128 1>; + interrupts = <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>; #address-cells = <1>; #size-cells = <0>; status = "disabled";
@@ -128,13 +130,13 @@ wdt: watchdog at 9900 { compatible = "amlogic,meson6-wdt"; reg = <0x9900 0x8>; - interrupts = <0 0 1>; + interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; }; timer at 9940 { compatible = "amlogic,meson6-timer"; reg = <0x9940 0x18>; - interrupts = <0 10 1>; + interrupts = <GIC_SPI 10 IRQ_TYPE_EDGE_RISING>; }; };
@@ -148,21 +150,21 @@ ir_receiver: ir-receiver at 480 { compatible= "amlogic,meson6-ir"; reg = <0x480 0x20>; - interrupts = <0 15 1>; + interrupts = <GIC_SPI 15 IRQ_TYPE_EDGE_RISING>; status = "disabled"; }; uart_AO: serial at 4c0 { compatible = "amlogic,meson-uart"; reg = <0x4c0 0x18>; - interrupts = <0 90 1>; + interrupts = <GIC_SPI 90 IRQ_TYPE_EDGE_RISING>; status = "disabled"; }; i2c_AO: i2c at 500 { compatible = "amlogic,meson6-i2c"; reg = <0x500 0x20>; - interrupts = <0 92 1>; + interrupts = <GIC_SPI 92 IRQ_TYPE_EDGE_RISING>; #address-cells = <1>; #size-cells = <0>; status = "disabled";
@@ -173,7 +175,7 @@ compatible = "amlogic,meson6-dwmac", "snps,dwmac"; reg = <0xc9410000 0x10000 0xc1108108 0x4>; - interrupts = <0 8 1>; + interrupts = <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>; interrupt-names = "macirq"; status = "disabled"; };
Signature · 1 line
2.13.1
Martin Blumenstingl
reviewerPATCH v2 3/10 ARM: dts: meson8: add the PWM_E and PWM_F pins
In reply to Martin BlumenstinglThis adds the definition of the PWM_E (CBUS) and PWM_F (AOBUS) to meson8.dtsi, allowing devices to use them. PWM_E can be used on some devices to generate the 32.768kHz clock for the SDIO wifi module, while PWM_F can be used to control the power LED.
--- arch/arm/boot/dts/meson8.dtsi | 14 ++++++++++++++ 1 file changed, 14 insertions(+)
arch/arm/boot/dts/meson8.dtsi +14 -0
@@ -123,6 +123,13 @@ function = "remote"; }; }; + + pwm_f_ao_pins: pwm-f-ao { + mux { + groups = "pwm_f_ao"; + function = "pwm_f_ao"; + }; + }; }; };
@@ -168,6 +175,13 @@ function = "ethernet"; }; }; + + pwm_e_pins: pwm-e { + mux { + groups = "pwm_e"; + function = "pwm_e"; + }; + }; }; };
Signature · 1 line
2.13.1
Martin Blumenstingl
reviewerPATCH v2 4/10 ARM: dts: meson8: add the pins for the SDIO controller
In reply to Martin Blumenstingl--- arch/arm/boot/dts/meson8.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+)
arch/arm/boot/dts/meson8.dtsi +24 -0
@@ -158,6 +158,30 @@ gpio-ranges = <&pinctrl_cbus 0 0 120>; }; + sd_a_pins: sd-a { + mux { + groups = "sd_d0_a", "sd_d1_a", "sd_d2_a", + "sd_d3_a", "sd_clk_a", "sd_cmd_a"; + function = "sd_a"; + }; + }; + + sd_b_pins: sd-b { + mux { + groups = "sd_d0_b", "sd_d1_b", "sd_d2_b", + "sd_d3_b", "sd_clk_b", "sd_cmd_b"; + function = "sd_b"; + }; + }; + + sd_c_pins: sd-c { + mux { + groups = "sd_d0_c", "sd_d1_c", "sd_d2_c", + "sd_d3_c", "sd_clk_c", "sd_cmd_c"; + function = "sd_c"; + }; + }; + spi_nor_pins: nor { mux { groups = "nor_d", "nor_q", "nor_c", "nor_cs";
Signature · 1 line
2.13.1
Martin Blumenstingl
reviewerPATCH v2 5/10 ARM: dts: meson: add the SAR ADC
In reply to Martin BlumenstinglThis adds the SAR ADC to meson.dtsi and configures the clocks on Meson8 and Meson8b to allow boards to use it. Some boards use it to connect a button to it.
--- arch/arm/boot/dts/meson.dtsi | 8 ++++++++ arch/arm/boot/dts/meson8.dtsi | 8 ++++++++ arch/arm/boot/dts/meson8b.dtsi | 8 ++++++++ 3 files changed, 24 insertions(+)
arch/arm/boot/dts/meson.dtsi +8 -0
@@ -103,6 +103,14 @@ status = "disabled"; }; + saradc: adc at 8680 { + compatible = "amlogic,meson-saradc"; + reg = <0x8680 0x34>; + #io-channel-cells = <1>; + interrupts = <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>; + status = "disabled"; + }; + uart_C: serial at 8700 { compatible = "amlogic,meson-uart"; reg = <0x8700 0x18>;
arch/arm/boot/dts/meson8.dtsi +8 -0
@@ -232,6 +232,14 @@ arm,filter-ranges = <0x100000 0xc0000000>; }; +&saradc { + compatible = "amlogic,meson8-saradc", "amlogic,meson-saradc"; + clocks = <&clkc CLKID_XTAL>, + <&clkc CLKID_SAR_ADC>, + <&clkc CLKID_SANA>; + clock-names = "clkin", "core", "sana"; +}; + &spifc { clocks = <&clkc CLKID_CLK81>; };
arch/arm/boot/dts/meson8b.dtsi +8 -0
@@ -177,6 +177,14 @@ arm,filter-ranges = <0x100000 0xc0000000>; }; +&saradc { + compatible = "amlogic,meson8b-saradc", "amlogic,meson-saradc"; + clocks = <&clkc CLKID_XTAL>, + <&clkc CLKID_SAR_ADC>, + <&clkc CLKID_SANA>; + clock-names = "clkin", "core", "sana"; +}; + &uart_AO { clocks = <&clkc CLKID_CLK81>; };
Signature · 1 line
2.13.1
Martin Blumenstingl
reviewerPATCH v2 6/10 ARM: dts: meson8: add reserved memory zones
In reply to Martin BlumenstinglThere seem to be two memory regions that need to be reserved, otherwise the system just hangs when running:
$ stress --vm-bytes $(awk '/MemFree/{printf "%d\n", $2 * 0.9;}' < /proc/meminfo)k \
--vm-keep -m 1The first memory region is really crucial and without it the system hangs. I could not find any references to this in Amlogic's GPL kernel sources.
The second region is used by the "suspend firmware". The u-boot sources (/arch/arm/cpu/aml_meson/m8/firmwareld.c) state that the suspend firmware is located at "64M + 15M" which matches CONFIG_MESON_SUSPEND in the Amlogic GPL kernel sources. The "suspend firmware" is responsible for waking up the system from suspend state.
This also fixes reading the full SD card as without this the system would simply hang (probably related to the first memory region, if some buffer is allocated there).
--- arch/arm/boot/dts/meson8.dtsi | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+)
arch/arm/boot/dts/meson8.dtsi +27 -0
@@ -83,6 +83,33 @@ reg = <0x203>; }; }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + /* 2 MiB reserved for Hardware ROM Firmware? */ + hwrom at 0 { + reg = <0x0 0x200000>; + no-map; + }; + + /* + * 1 MiB reserved for the "ARM Power Firmware": this is ARM + * code which is responsible for system suspend. It loads a + * piece of ARC code ("arc_power" in the vendor u-boot tree) + * into SRAM, executes that and shuts down the (last) ARM core. + * The arc_power firmware then checks various wakeup sources + * (IR remote receiver, HDMI CEC, WIFI and Bluetooth wakeup or + * simply the power key) and re-starts the ARM core once it + * detects a wakeup request. + */ + power-firmware at 4f00000 { + reg = <0x4f00000 0x100000>; + no-map; + }; + }; }; /* end of / */ &aobus {
Signature · 1 line
2.13.1
Martin Blumenstingl
reviewerPATCH v2 7/10 ARM: dts: meson: add the hardware random number generator
In reply to Martin BlumenstinglAll supported Meson SoCs have a random number generator in CBUS. Newer SoCs (GXBB, GXL and GXM) provide only one 32-bit random number register, whereas the older SoCs (Meson6, Meson8 and Meson8b) have two 32-bit random number registers. The existing meson-rng driver only supports the lower 32-bit - but it still works fine on the older SoCs apart from this small limitation.
--- arch/arm/boot/dts/meson.dtsi | 5 +++++ arch/arm/boot/dts/meson8.dtsi | 6 ++++++ arch/arm/boot/dts/meson8b.dtsi | 6 ++++++ 3 files changed, 17 insertions(+)
arch/arm/boot/dts/meson.dtsi +5 -0
@@ -80,6 +80,11 @@ #size-cells = <1>; ranges = <0x0 0xc1100000 0x200000>; + hwrng: rng at 8100 { + compatible = "amlogic,meson-rng"; + reg = <0x8100 0x8>; + }; + uart_A: serial at 84c0 { compatible = "amlogic,meson-uart"; reg = <0x84c0 0x18>;
arch/arm/boot/dts/meson8.dtsi +6 -0
@@ -241,6 +241,12 @@ clock-names = "stmmaceth"; }; +&hwrng { + compatible = "amlogic,meson8-rng", "amlogic,meson-rng"; + clocks = <&clkc CLKID_RNG0>; + clock-names = "core"; +}; + &i2c_AO { clocks = <&clkc CLKID_CLK81>; };
arch/arm/boot/dts/meson8b.dtsi +6 -0
@@ -171,6 +171,12 @@ }; }; +&hwrng { + compatible = "amlogic,meson8b-rng", "amlogic,meson-rng"; + clocks = <&clkc CLKID_RNG0>; + clock-names = "core"; +}; + &L2 { arm,data-latency = <3 3 3>; arm,tag-latency = <2 2 2>;
Signature · 1 line
2.13.1
Martin Blumenstingl
reviewerPATCH v2 8/10 ARM: dts: meson: add USB support on Meson8 and Meson8b
In reply to Martin BlumenstinglThis adds the DWC2 USB controller nodes and the corresponding USB2 PHY nodes to meson.dtsi (as the same - or at least a very similar) IP block is used on all SoCs (at the same physical address). Additionally meson8.dtsi and meson8b.dtsi add the required clocks to the DWC2 and USB2 PHY nodes, otherwise the DWC2 controller cannot be initialized by the dwc2 driver.
--- arch/arm/boot/dts/meson.dtsi | 38 ++++++++++++++++++++++++++++++++++++++ arch/arm/boot/dts/meson8.dtsi | 24 ++++++++++++++++++++++++ arch/arm/boot/dts/meson8b.dtsi | 26 ++++++++++++++++++++++++++ 3 files changed, 88 insertions(+)
arch/arm/boot/dts/meson.dtsi +38 -0
@@ -132,6 +132,20 @@ status = "disabled"; }; + usb0_phy: phy at 8800 { + compatible = "amlogic,meson-mx-usb2-phy"; + #phy-cells = <0>; + reg = <0x8800 0x20>; + status = "disabled"; + }; + + usb1_phy: phy at 8820 { + compatible = "amlogic,meson-mx-usb2-phy"; + #phy-cells = <0>; + reg = <0x8820 0x20>; + status = "disabled"; + }; + spifc: spi at 8c80 { compatible = "amlogic,meson6-spifc"; reg = <0x8c80 0x80>;
@@ -184,6 +198,30 @@ }; }; + usb0: usb at c9040000 { + compatible = "snps,dwc2"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xc9040000 0x40000>; + interrupts = <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>; + phys = <&usb0_phy>; + phy-names = "usb2-phy"; + dr_mode = "host"; + status = "disabled"; + }; + + usb1: usb at c90c0000 { + compatible = "snps,dwc2"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xc90c0000 0x40000>; + interrupts = <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>; + phys = <&usb1_phy>; + phy-names = "usb2-phy"; + dr_mode = "host"; + status = "disabled"; + }; + ethmac: ethernet at c9410000 { compatible = "amlogic,meson6-dwmac", "snps,dwmac"; reg = <0xc9410000 0x10000
arch/arm/boot/dts/meson8.dtsi +24 -0
@@ -292,3 +292,27 @@ &uart_C { clocks = <&clkc CLKID_CLK81>; }; + +&usb0 { + compatible = "amlogic,meson8-usb", "snps,dwc2"; + clocks = <&clkc CLKID_USB0_DDR_BRIDGE>; + clock-names = "otg"; +}; + +&usb1 { + compatible = "amlogic,meson8-usb", "snps,dwc2"; + clocks = <&clkc CLKID_USB1_DDR_BRIDGE>; + clock-names = "otg"; +}; + +&usb0_phy { + compatible = "amlogic,meson8-usb2-phy", "amlogic,meson-mx-usb2-phy"; + clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>; + clock-names = "usb_general", "usb"; +}; + +&usb1_phy { + compatible = "amlogic,meson8-usb2-phy", "amlogic,meson-mx-usb2-phy"; + clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>; + clock-names = "usb_general", "usb"; +};
arch/arm/boot/dts/meson8b.dtsi +26 -0
@@ -206,3 +206,29 @@ &uart_C { clocks = <&clkc CLKID_CLK81>; }; + +&usb0 { + compatible = "amlogic,meson8b-usb", "snps,dwc2"; + clocks = <&clkc CLKID_USB0_DDR_BRIDGE>; + clock-names = "otg"; +}; + +&usb1 { + compatible = "amlogic,meson8b-usb", "snps,dwc2"; + clocks = <&clkc CLKID_USB1_DDR_BRIDGE>; + clock-names = "otg"; +}; + +&usb0_phy { + compatible = "amlogic,meson8b-usb2-phy", "amlogic,meson-mx-usb2-phy"; + clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>; + clock-names = "usb_general", "usb"; + resets = <&reset RESET_USB_OTG>; +}; + +&usb1_phy { + compatible = "amlogic,meson8b-usb2-phy", "amlogic,meson-mx-usb2-phy"; + clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>; + clock-names = "usb_general", "usb"; + resets = <&reset RESET_USB_OTG>; +};
Signature · 1 line
2.13.1
Martin Blumenstingl
reviewerPATCH v2 9/10 ARM: dts: meson8b: add the SCU device node
In reply to Martin BlumenstinglAmlogic's Meson8b SoC has a Snoop Control Unit (SCU), just like many other Cortex-A5 SoCs. Add the corresponding devicetree node so it can be used during SMP boot.
--- arch/arm/boot/dts/meson8.dtsi | 5 +++++ arch/arm/boot/dts/meson8b.dtsi | 5 +++++ 2 files changed, 10 insertions(+)
arch/arm/boot/dts/meson8.dtsi +5 -0
@@ -110,6 +110,11 @@ no-map; }; }; + + scu at c4300000 { + compatible = "arm,cortex-a9-scu"; + reg = <0xc4300000 0x100>; + }; }; /* end of / */ &aobus {
arch/arm/boot/dts/meson8b.dtsi +5 -0
@@ -82,6 +82,11 @@ reg = <0x203>; }; }; + + scu at c4300000 { + compatible = "arm,cortex-a5-scu"; + reg = <0xc4300000 0x100>; + }; }; /* end of / */ &aobus {
Signature · 1 line
2.13.1
Martin Blumenstingl
reviewerPATCH v2 10/10 ARM: dts: meson: use the real ethernet clock on Meson8 and Meson8b
In reply to Martin BlumenstinglUntil now clk81 was used as gate clock for the ethernet controller on Meson8 whereas Meson8b did not configure a gate clock at all. Use CLKID_ETH for both SoCs, which is the real gate clock for the ethernet controller.
--- arch/arm/boot/dts/meson8.dtsi | 2 +- arch/arm/boot/dts/meson8b.dtsi | 5 +++++ 2 files changed, 6 insertions(+), 1 deletion(-)
arch/arm/boot/dts/meson8.dtsi +1 -1
@@ -242,7 +242,7 @@ }; ðmac { - clocks = <&clkc CLKID_CLK81>; + clocks = <&clkc CLKID_ETH>; clock-names = "stmmaceth"; };
arch/arm/boot/dts/meson8b.dtsi +5 -0
@@ -176,6 +176,11 @@ }; }; +ðmac { + clocks = <&clkc CLKID_ETH>; + clock-names = "stmmaceth"; +}; + &hwrng { compatible = "amlogic,meson8b-rng", "amlogic,meson-rng"; clocks = <&clkc CLKID_RNG0>;
Signature · 1 line
2.13.1
Kevin Hilman
maintainerv2 cover add support for more devices on Meson8 and Meson8b
In reply to Martin BlumenstinglQuoted 23 lines · Martin Blumenstingl
This series adds:
- USB support on Meson8 and Meson8b (it seems that some boards show an error when trying to initialize one of the USB2 PHYs, but we have the same problem on some GXBB boards. it is working fine for me - on a board which is not supported upstream yet)
- hardware random number generator support (Meson8 and Meson8b seem to have two 32-bit hardware random number generator registers, while the GX SoCs only have one. This is not handled by the meson-rng driver yet, but that can still be improved later on)
- SAR ADC support
- add reserved memory zones to fix random hangs when filling the memory (currently only on Meson8 until I have a Meson8b device to test if the same problem appears there as well)
- use the real ethernet clock on Meson8 and Meson8b to fix ethernet when the bootloader does not enable the gate clock
- add the SCU (Snoop Control Unit) which is needed for SMP support
- minor preparations for further .dts updates as this already exports the SDIO clocks (a driver for this MMC controller is work-in-progress) as well as the corresponding pin definitions inmeson8.dtsi
- this adds thepwm_e(typically used for the 32.768 kHz LPO clock for the SDIO wifi chip) andpwm_f(used on some boards for the dimmable power LED) pins tomeson8.dtsi
Quoted 2 lines
NOTE: the .dts changes from this series depend on my previous patch from [0]: "ARM: dts: meson8: fix the IR receiver pins"
Thanks for the reminder, I had missed that one.
This series now applied to v4.13/dt (after merging in the clock headers deps from Jerome) and will go in the 2nd round of pull requests to arm-soc, probably early next week.
Thanks for the continued great work Martin!
Kevin
Kevin Hilman
maintainerv2 cover add support for more devices on Meson8 and Meson8b
In reply to Martin BlumenstinglQuoted 14 lines · Martin Blumenstingl
This series adds:
- USB support on Meson8 and Meson8b (it seems that some boards show an error when trying to initialize one of the USB2 PHYs, but we have the same problem on some GXBB boards. it is working fine for me - on a board which is not supported upstream yet)
- hardware random number generator support (Meson8 and Meson8b seem to have two 32-bit hardware random number generator registers, while the GX SoCs only have one. This is not handled by the meson-rng driver yet, but that can still be improved later on)
- SAR ADC support
- add reserved memory zones to fix random hangs when filling the memory (currently only on Meson8 until I have a Meson8b device to test if the same problem appears there as well)
- use the real ethernet clock on Meson8 and Meson8b to fix ethernet when
Quoted 8 lines
the bootloader does not enable the gate clock
- add the SCU (Snoop Control Unit) which is needed for SMP support
- minor preparations for further .dts updates as this already exports the SDIO clocks (a driver for this MMC controller is work-in-progress) as well as the corresponding pin definitions inmeson8.dtsi
- this adds thepwm_e(typically used for the 32.768 kHz LPO clock for the SDIO wifi chip) andpwm_f(used on some boards for the dimmable power LED) pins tomeson8.dtsi
Oh, one minor nit... When you send a v2 of a series, please start a new thread. You sent this one in-reply-to the original series. When you do that, it risks getting missed when I mark the previous series as read.
Thanks,
Kevin
Martin Blumenstingl
reviewerv2 cover add support for more devices on Meson8 and Meson8b
Hi Kevin,
Quoted 25 lines · Kevin Hilman
Quoted 14 lines · Martin Blumenstingl
This series adds:
- USB support on Meson8 and Meson8b (it seems that some boards show an error when trying to initialize one of the USB2 PHYs, but we have the same problem on some GXBB boards. it is working fine for me - on a board which is not supported upstream yet)
- hardware random number generator support (Meson8 and Meson8b seem to have two 32-bit hardware random number generator registers, while the GX SoCs only have one. This is not handled by the meson-rng driver yet, but that can still be improved later on)
- SAR ADC support
- add reserved memory zones to fix random hangs when filling the memory (currently only on Meson8 until I have a Meson8b device to test if the same problem appears there as well)
- use the real ethernet clock on Meson8 and Meson8b to fix ethernet whenQuoted 8 lines
the bootloader does not enable the gate clock
- add the SCU (Snoop Control Unit) which is needed for SMP support
- minor preparations for further .dts updates as this already exports the SDIO clocks (a driver for this MMC controller is work-in-progress) as well as the corresponding pin definitions inmeson8.dtsi
- this adds thepwm_e(typically used for the 32.768 kHz LPO clock for the SDIO wifi chip) andpwm_f(used on some boards for the dimmable power LED) pins tomeson8.dtsi
Quoted 3 lines
Oh, one minor nit... When you send a v2 of a series, please start a new thread. You sent this one in-reply-to the original series. When you do that, it risks getting missed when I mark the previous series as read.
oh, thanks for letting me know - I though that sending the update as reply was "good practice"! noted for the next batch of changes :)
Quoted 1 line
Thanks,
you're welcome - it's nice to put all these puzzle pieces together to get a specific SoC from "there's output on the serial console and Linux boots" to "now you can use USB, the SD card slot, ADC, ..."
Regards,
Martin