use the Meson8b clock controller driver on Meson8 SoCs

The clock controller on Meson8, Meson8b and Meson8m2 is very similar based on the code from the Amlogic GPL kernel sources. Add separate compatibles for each SoC to make sure that we can easily implement all the small differences for each SoC later on.

In general the Meson8 and Meson8m2 seem to be almost identical as they even share the same mach-meson8 directory in Amlogic's GPL kernel sources.
The main clocks on Meson8, Meson8b and Meson8m2 are very similar, because they are all using the same PLL values, 90% of the clock gates are the same (the actual diffstat of the mach-meson8/clock.c and mach-meson8b/clock.c files is around 30 to 40 lines, when excluding all commented out code).
The difference between the Meson8 and Meson8b clock gates seem to be:
- Meson8 has AIU_PCLK, HDMI_RX, VCLK2_ENCT, VCLK2_ENCL, UART3, ? CSI_DIG_CLKIN gates which don't seem to be available on Meson8b
- the gate on Meson8 for bit 7 seems to be named "_1200XXX" instead ? of "PERIPHS_TOP" (on Meson8b)
- Meson8b has a SANA gate which doesn't seem to exist on Meson8 (or ? on Meson8 the same bit is used by the UART3 gate in Amlogic's GPL ? kernel sources)
None of these gates is added for now, since it's unclear whether these definitions are actually correct (the VCLK2_ENCT gate for example is defined, but only used in some commented block).

The main difference between all three SoCs seem to be the video (VPU) clocks. Apart from different supported clock rates (according to vpu.c in mach-meson8 and mach-meson8b from Amlogic's GPL kernel sources) the most notable difference is that Meson8m2 has a GP_PLL clock and a mux (probably the same as on the Meson GX SoCs) to support glitch-free (clock rate) switching.
None of these VPU clocks are not supported by our mainline meson8b clock driver yet though.

Signed-off-by Martin Blumenstingl <[email protected]>

---
?.../devicetree/bindings/clock/amlogic,meson8b-clkc.txt????????| 11 +++++++---

- ?drivers/clk/meson/Kconfig?????????????????????????????????????|??6 +++--- ?drivers/clk/meson/meson8b.c???????????????????????????????????|??5 ++++-

?3 files changed, 14 insertions(+), 8 deletions(-)

Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt +1 -1

index 2b7b3fa588d7..606da38c0959 100644
@@ -1,11 +1,14 @@
-* Amlogic Meson8b Clock and Reset Unit
+* Amlogic Meson8, Meson8b and Meson8m2 Clock and Reset Unit

?

Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt +2 -2

-The Amlogic Meson8b clock controller generates and supplies clock to various
-controllers within the SoC.
+The Amlogic Meson8 / Meson8b / Meson8m2 clock controller generates and
+supplies clock to various controllers within the SoC.

?
?Required Properties:
?
-- compatible: should be "amlogic,meson8b-clkc"
+- compatible: must be one of:

Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt +3 -0

+	- "amlogic,meson8-clkc" for Meson8 (S802) SoCs
+	- "amlogic,meson8b-clkc" for Meson8 (S805) SoCs
+	- "amlogic,meson8m2-clkc" for Meson8m2 (S812) SoCs

?- reg: it must be composed by two tuples:
? 0) physical base address of the xtal register and length of memory
? ???mapped region.

drivers/clk/meson/Kconfig +0 -0

index 19480bcc7046..4a806203b73c 100644
@@ -7,9 +7,9 @@ config COMMON_CLK_MESON8B

? bool
? depends on COMMON_CLK_AMLOGIC
? help

drivers/clk/meson/Kconfig +3 -3

-	??Support for the clock controller on AmLogic S805 devices, aka
-	??meson8b. Say Y if you want peripherals and CPU frequency scaling to
-	??work.
+	??Support for the clock controller on AmLogic S802 (Meson8),
+	??S805 (Meson8b) and S812 (Meson8m2) devices. Say Y if you
+	??want peripherals and CPU frequency scaling to work.

?
?config COMMON_CLK_GXBB
? bool

drivers/clk/meson/meson8b.c +0 -0

index bfd1690724de..94c55e79cdde 100644
@@ -1,5 +1,6 @@

?/*
- * AmLogic S805 / Meson8b Clock Controller Driver
+ * AmLogic S802 (Meson8) / S805 (Meson8b) / S812 (Meson8m2) Clock Controller
+ * Driver
? *
? * Copyright (c) 2015 Endless Mobile, Inc.
? * Author: Carlo Caione <[email protected]>

drivers/clk/meson/meson8b.c +0 -0

@@ -777,7 +778,9 @@ static int meson8b_clkc_probe(struct platform_device
 *pdev)
 ?}

?
?static const struct of_device_id meson8b_clkc_match_table[] = {

drivers/clk/meson/meson8b.c +1 -0

+	{ .compatible = "amlogic,meson8-clkc" },

? { .compatible = "amlogic,meson8b-clkc" },

drivers/clk/meson/meson8b.c +1 -0

+	{ .compatible = "amlogic,meson8m2-clkc" },

? { }
?};
?

Quoted 34 lines · Martin Blumenstingl

The clock controller on Meson8, Meson8b and Meson8m2 is very similar based on the code from the Amlogic GPL kernel sources. Add separate compatibles for each SoC to make sure that we can easily implement all the small differences for each SoC later on.

In general the Meson8 and Meson8m2 seem to be almost identical as they even share the same mach-meson8 directory in Amlogic's GPL kernel sources.
The main clocks on Meson8, Meson8b and Meson8m2 are very similar, because they are all using the same PLL values, 90% of the clock gates are the same (the actual diffstat of the mach-meson8/clock.c and mach-meson8b/clock.c files is around 30 to 40 lines, when excluding all commented out code).
The difference between the Meson8 and Meson8b clock gates seem to be:
- Meson8 has AIU_PCLK, HDMI_RX, VCLK2_ENCT, VCLK2_ENCL, UART3, CSI_DIG_CLKIN gates which don't seem to be available on Meson8b
- the gate on Meson8 for bit 7 seems to be named "_1200XXX" instead of "PERIPHS_TOP" (on Meson8b)
- Meson8b has a SANA gate which doesn't seem to exist on Meson8 (or on Meson8 the same bit is used by the UART3 gate in Amlogic's GPL kernel sources)
None of these gates is added for now, since it's unclear whether these definitions are actually correct (the VCLK2_ENCT gate for example is defined, but only used in some commented block).

The main difference between all three SoCs seem to be the video (VPU) clocks. Apart from different supported clock rates (according to vpu.c in mach-meson8 and mach-meson8b from Amlogic's GPL kernel sources) the most notable difference is that Meson8m2 has a GP_PLL clock and a mux (probably the same as on the Meson GX SoCs) to support glitch-free (clock rate) switching.
None of these VPU clocks are not supported by our mainline meson8b clock driver yet though.

Quoted 3 lines

Signed-off-by Martin Blumenstingl <[email protected]>

---
 .../devicetree/bindings/clock/amlogic,meson8b-clkc.txt        | 11 +++++++---

I think you should split the binding documentation and clk changes into separate patches.

Quoted 3 lines

-

 drivers/clk/meson/Kconfig                                     |  6 +++---
 drivers/clk/meson/meson8b.c                                   |  5 ++++-

The change being more platform than clock related, I'd prefer if Kevin or Carlo ack it before we apply it.

Apart from this, the change looks good to me. Nice to see people taking interest
in these SoCs. Would you mind telling us a bit more about the board you have
used for this task and the tests you have done ? It would maybe allow other people to help you.

Cheers
Jerome

Quoted 59 lines

 3 files changed, 14 insertions(+), 8 deletions(-)

Documentation/devicetree/bindings/clock/amlogic,meson8b-clkc.txt +7 -4

index 2b7b3fa588d7..606da38c0959 100644
@@ -1,11 +1,14 @@
-* Amlogic Meson8b Clock and Reset Unit
+* Amlogic Meson8, Meson8b and Meson8m2 Clock and Reset Unit
 
-The Amlogic Meson8b clock controller generates and supplies clock to various
-controllers within the SoC.
+The Amlogic Meson8 / Meson8b / Meson8m2 clock controller generates and
+supplies clock to various controllers within the SoC.
 
 Required Properties:
 
-- compatible: should be "amlogic,meson8b-clkc"
+- compatible: must be one of:
+     - "amlogic,meson8-clkc" for Meson8 (S802) SoCs
+     - "amlogic,meson8b-clkc" for Meson8 (S805) SoCs
+     - "amlogic,meson8m2-clkc" for Meson8m2 (S812) SoCs
 - reg: it must be composed by two tuples:
      0) physical base address of the xtal register and length of memory
         mapped region.

drivers/clk/meson/Kconfig +3 -3

index 19480bcc7046..4a806203b73c 100644
@@ -7,9 +7,9 @@ config COMMON_CLK_MESON8B
      bool
      depends on COMMON_CLK_AMLOGIC
      help
-       Support for the clock controller on AmLogic S805 devices, aka
-       meson8b. Say Y if you want peripherals and CPU frequency scaling to
-       work.
+       Support for the clock controller on AmLogic S802 (Meson8),
+       S805 (Meson8b) and S812 (Meson8m2) devices. Say Y if you
+       want peripherals and CPU frequency scaling to work.
 
 config COMMON_CLK_GXBB
      bool

drivers/clk/meson/meson8b.c +2 -1

index bfd1690724de..94c55e79cdde 100644
@@ -1,5 +1,6 @@
 /*
- * AmLogic S805 / Meson8b Clock Controller Driver
+ * AmLogic S802 (Meson8) / S805 (Meson8b) / S812 (Meson8m2) Clock Controller
+ * Driver
  *
  * Copyright (c) 2015 Endless Mobile, Inc.
  * Author: Carlo Caione <[email protected]>

@@ -777,7 +778,9 @@ static int meson8b_clkc_probe(struct platform_device
 *pdev)
 }
 

drivers/clk/meson/meson8b.c static int meson8b_clkc_probe(struct platform_device *pdev) · line 785

Quoted 7 lines

drivers/clk/meson/meson8b.c +2 -0

 static const struct of_device_id meson8b_clkc_match_table[] = {
+     { .compatible = "amlogic,meson8-clkc" },
      { .compatible = "amlogic,meson8b-clkc" },
+     { .compatible = "amlogic,meson8m2-clkc" },
      { }
 };

Quoted 3 lines

I think you should split the binding documentation and clk changes into separate
patches.

OK, from what I know is that for "trivial" changes the driver and dt-binding changes can go through one patch.
this patch started as a four-line patch which added two lines of documentation and two lines of driver code.

however, with all the Kconfig/comment/etc updates I think that you are right and it's worth splitting this into two patches (one for the clock driver and one for the dt-binding changes)

Quoted 8 lines · Martin Blumenstingl

Quoted 3 lines

I think you should split the binding documentation and clk changes into separate
patches.

OK, from what I know is that for "trivial" changes the driver and dt-binding changes can go through one patch.
this patch started as a four-line patch which added two lines of documentation and two lines of driver code.

I'm not aware of such tolerance but if you've have seen that the DT maintainers are OK with it, feel free to point me to it.

Last time I heard about it, DT guys were using filter-branch on the kernel tree to create a separate tree, so I was thinking that this "documentation as a separate patch" was a hard rule ... but I may be wrong

Quoted 34 lines · Martin Blumenstingl

The clock controller on Meson8, Meson8b and Meson8m2 is very similar based on the code from the Amlogic GPL kernel sources. Add separate compatibles for each SoC to make sure that we can easily implement all the small differences for each SoC later on.

In general the Meson8 and Meson8m2 seem to be almost identical as they even share the same mach-meson8 directory in Amlogic's GPL kernel sources.
The main clocks on Meson8, Meson8b and Meson8m2 are very similar, because they are all using the same PLL values, 90% of the clock gates are the same (the actual diffstat of the mach-meson8/clock.c and mach-meson8b/clock.c files is around 30 to 40 lines, when excluding all commented out code).
The difference between the Meson8 and Meson8b clock gates seem to be:
- Meson8 has AIU_PCLK, HDMI_RX, VCLK2_ENCT, VCLK2_ENCL, UART3, ? CSI_DIG_CLKIN gates which don't seem to be available on Meson8b
- the gate on Meson8 for bit 7 seems to be named "_1200XXX" instead ? of "PERIPHS_TOP" (on Meson8b)
- Meson8b has a SANA gate which doesn't seem to exist on Meson8 (or ? on Meson8 the same bit is used by the UART3 gate in Amlogic's GPL ? kernel sources)
None of these gates is added for now, since it's unclear whether these definitions are actually correct (the VCLK2_ENCT gate for example is defined, but only used in some commented block).

The main difference between all three SoCs seem to be the video (VPU) clocks. Apart from different supported clock rates (according to vpu.c in mach-meson8 and mach-meson8b from Amlogic's GPL kernel sources) the most notable difference is that Meson8m2 has a GP_PLL clock and a mux (probably the same as on the Meson GX SoCs) to support glitch-free (clock rate) switching.
None of these VPU clocks are not supported by our mainline meson8b clock driver yet though.

Quoted 3 lines

Signed-off-by Martin Blumenstingl <[email protected]>

---
?.../devicetree/bindings/clock/amlogic,meson8b-clkc.txt????????| 11 +++++++---

I think you should split the binding documentation and clk changes into separate patches.

Quoted 3 lines

- ?drivers/clk/meson/Kconfig?????????????????????????????????????|??6 +++--- ?drivers/clk/meson/meson8b.c???????????????????????????????????|??5 ++++-

The change being more platform than clock related, I'd prefer if Kevin or Carlo ack it before we apply it.

Quoted 48 lines · Jerome Brunet

Quoted 34 lines · Martin Blumenstingl

The clock controller on Meson8, Meson8b and Meson8m2 is very similar based on the code from the Amlogic GPL kernel sources. Add separate compatibles for each SoC to make sure that we can easily implement all the small differences for each SoC later on.

In general the Meson8 and Meson8m2 seem to be almost identical as they even share the same mach-meson8 directory in Amlogic's GPL kernel sources.
The main clocks on Meson8, Meson8b and Meson8m2 are very similar, because they are all using the same PLL values, 90% of the clock gates are the same (the actual diffstat of the mach-meson8/clock.c and mach-meson8b/clock.c files is around 30 to 40 lines, when excluding all commented out code).
The difference between the Meson8 and Meson8b clock gates seem to be:
- Meson8 has AIU_PCLK, HDMI_RX, VCLK2_ENCT, VCLK2_ENCL, UART3, ? CSI_DIG_CLKIN gates which don't seem to be available on Meson8b
- the gate on Meson8 for bit 7 seems to be named "_1200XXX" instead ? of "PERIPHS_TOP" (on Meson8b)
- Meson8b has a SANA gate which doesn't seem to exist on Meson8 (or ? on Meson8 the same bit is used by the UART3 gate in Amlogic's GPL ? kernel sources)
None of these gates is added for now, since it's unclear whether these definitions are actually correct (the VCLK2_ENCT gate for example is defined, but only used in some commented block).

The main difference between all three SoCs seem to be the video (VPU) clocks. Apart from different supported clock rates (according to vpu.c in mach-meson8 and mach-meson8b from Amlogic's GPL kernel sources) the most notable difference is that Meson8m2 has a GP_PLL clock and a mux (probably the same as on the Meson GX SoCs) to support glitch-free (clock rate) switching.
None of these VPU clocks are not supported by our mainline meson8b clock driver yet though.

Quoted 4 lines

Signed-off-by Martin Blumenstingl <[email protected]>

---
?.../devicetree/bindings/clock/amlogic,meson8b-clkc.txt????????| 11
+++++++---

I think you should split the binding documentation and clk changes into separate
patches.

Quoted 3 lines

- ?drivers/clk/meson/Kconfig?????????????????????????????????????|??6 +++--- ?drivers/clk/meson/meson8b.c???????????????????????????????????|??5 ++++-

Quoted 3 lines

The change being more platform than clock related, I'd prefer if Kevin or Carlo
ack it before we apply it.

Acked-by Kevin Hilman <[email protected]>

Select COMMON_CLK_MESON8B also for MACH_MESON8 since the Meson8b clock controller driver can also be used on Meson8 SoCs now that we have a separate compatible for it.

Signed-off-by Martin Blumenstingl <[email protected]>

---
?arch/arm/mach-meson/Kconfig | 1 +
?1 file changed, 1 insertion(+)

arch/arm/mach-meson/Kconfig +0 -0

index b6e3acc63e14..ee30511849ca 100644
@@ -21,6 +21,7 @@ config MACH_MESON8

? bool "Amlogic Meson8 SoCs support"
? default ARCH_MESON
? select MESON6_TIMER

arch/arm/mach-meson/Kconfig +1 -0

+	select COMMON_CLK_MESON8B

?
?config MACH_MESON8B
? bool "Amlogic Meson8b SoCs support"

Quoted 5 lines · Martin Blumenstingl

Select COMMON_CLK_MESON8B also for MACH_MESON8 since the Meson8b clock controller driver can also be used on Meson8 SoCs now that we have a separate compatible for it.

Signed-off-by Martin Blumenstingl <[email protected]>

Acked-by Jerome Brunet <[email protected]>

This removes the dummy clk81 gate and replaces it with the actual clock controller's CLKID_CLK81. This will also allow us to pass the real clock IDs to all devices where the clock is controlled by clkc in the future.

Signed-off-by Martin Blumenstingl <[email protected]>

---
?arch/arm/boot/dts/meson8.dtsi | 32 ++++++++++++++++---------------- ?1 file changed, 16 insertions(+), 16 deletions(-)

arch/arm/boot/dts/meson8.dtsi +0 -0

index 6993077331c7..9b0b3ddbb17e 100644
@@ -43,6 +43,7 @@

? *?????OTHER DEALINGS IN THE SOFTWARE.
? */
?
+#include <dt-bindings/clock/meson8b-clkc.h>
?#include <dt-bindings/gpio/meson8-gpio.h>
?/include/ "meson.dtsi"
?

arch/arm/boot/dts/meson8.dtsi +0 -7

@@ -82,13 +83,6 @@
 ?			reg = <0x203>;
 ?		};
 ?	};
-
-	clk81: clk at 0 {
-		#clock-cells = <0>;
-		compatible = "fixed-clock";
-		clock-frequency = <141666666>;
-	};
-

?}; /* end of / */
?
?&aobus {

arch/arm/boot/dts/meson8.dtsi +0 -0

@@ -126,6 +120,12 @@
 ?};

?
?&cbus {

arch/arm/boot/dts/meson8.dtsi +6 -0

+	clkc: clock-controller at 4000 {
+		#clock-cells = <1>;
+		compatible = "amlogic,meson8-clkc";
+		reg = <0x8000 0x4>, <0x4000 0x460>;
+	};
+

? pinctrl_cbus: pinctrl at 9880 {
? compatible = "amlogic,meson8-cbus-pinctrl";
? reg = <0x9880 0x10>;

arch/arm/boot/dts/meson8.dtsi +0 -0

@@ -172,20 +172,20 @@
 ?};

?
?&ethmac {

arch/arm/boot/dts/meson8.dtsi +1 -1

-	clocks = <&clk81>;
+	clocks = <&clkc CLKID_CLK81>;

? clock-names = "stmmaceth";
?};
?
?&i2c_AO {

arch/arm/boot/dts/meson8.dtsi +1 -1

-	clocks = <&clk81>;
+	clocks = <&clkc CLKID_CLK81>;

?};
?
?&i2c_A {

arch/arm/boot/dts/meson8.dtsi +1 -1

-	clocks = <&clk81>;
+	clocks = <&clkc CLKID_CLK81>;

?};
?
?&i2c_B {

arch/arm/boot/dts/meson8.dtsi +1 -1

-	clocks = <&clk81>;
+	clocks = <&clkc CLKID_CLK81>;

?};
?
?&L2 {

arch/arm/boot/dts/meson8.dtsi +0 -0

@@ -195,21 +195,21 @@
 ?};

?
?&spifc {

arch/arm/boot/dts/meson8.dtsi +1 -1

-	clocks = <&clk81>;
+	clocks = <&clkc CLKID_CLK81>;

?};
?
?&uart_AO {

arch/arm/boot/dts/meson8.dtsi +1 -1

-	clocks = <&clk81>;
+	clocks = <&clkc CLKID_CLK81>;

?};
?
?&uart_A {

arch/arm/boot/dts/meson8.dtsi +1 -1

-	clocks = <&clk81>;
+	clocks = <&clkc CLKID_CLK81>;

?};
?
?&uart_B {

arch/arm/boot/dts/meson8.dtsi +1 -1

-	clocks = <&clk81>;
+	clocks = <&clkc CLKID_CLK81>;

?};
?
?&uart_C {

arch/arm/boot/dts/meson8.dtsi +1 -1

-	clocks = <&clk81>;
+	clocks = <&clkc CLKID_CLK81>;

?};

Quoted 5 lines · Martin Blumenstingl

This removes the dummy clk81 gate and replaces it with the actual clock controller's CLKID_CLK81. This will also allow us to pass the real clock IDs to all devices where the clock is controlled by clkc in the future.

Signed-off-by Martin Blumenstingl <[email protected]>

This is going in the right direction and at least align meson8 and meson8b.

Acked-by Jerome Brunet <[email protected]>

Later on, I'm wondering if some of these clock assignments should be moved to meson.dtsi ? meson8.dtsi and meson8b.dtsi look very similar

Quoted 95 lines

---
 arch/arm/boot/dts/meson8.dtsi | 32 ++++++++++++++++----------------
 1 file changed, 16 insertions(+), 16 deletions(-)

arch/arm/boot/dts/meson8.dtsi +16 -16

index 6993077331c7..9b0b3ddbb17e 100644
@@ -43,6 +43,7 @@
  *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
+#include <dt-bindings/clock/meson8b-clkc.h>
 #include <dt-bindings/gpio/meson8-gpio.h>
 /include/ "meson.dtsi"
 

@@ -82,13 +83,6 @@
                      reg = <0x203>;
              };
      };
-
-     clk81: clk at 0 {
-             #clock-cells = <0>;
-             compatible = "fixed-clock";
-             clock-frequency = <141666666>;
-     };
-
 }; /* end of / */
 
 &aobus {

@@ -126,6 +120,12 @@
 };
 
 &cbus {
+     clkc: clock-controller at 4000 {
+             #clock-cells = <1>;
+             compatible = "amlogic,meson8-clkc";
+             reg = <0x8000 0x4>, <0x4000 0x460>;
+     };
+
      pinctrl_cbus: pinctrl at 9880 {
              compatible = "amlogic,meson8-cbus-pinctrl";
              reg = <0x9880 0x10>;

@@ -172,20 +172,20 @@
 };
 
 &ethmac {
-     clocks = <&clk81>;
+     clocks = <&clkc CLKID_CLK81>;
      clock-names = "stmmaceth";
 };
 
 &i2c_AO {
-     clocks = <&clk81>;
+     clocks = <&clkc CLKID_CLK81>;
 };
 
 &i2c_A {
-     clocks = <&clk81>;
+     clocks = <&clkc CLKID_CLK81>;
 };
 
 &i2c_B {
-     clocks = <&clk81>;
+     clocks = <&clkc CLKID_CLK81>;
 };
 
 &L2 {

@@ -195,21 +195,21 @@
 };
 
 &spifc {
-     clocks = <&clk81>;
+     clocks = <&clkc CLKID_CLK81>;
 };
 
 &uart_AO {
-     clocks = <&clk81>;
+     clocks = <&clkc CLKID_CLK81>;
 };
 
 &uart_A {
-     clocks = <&clk81>;
+     clocks = <&clkc CLKID_CLK81>;
 };
 
 &uart_B {
-     clocks = <&clk81>;
+     clocks = <&clkc CLKID_CLK81>;
 };
 
 &uart_C {
-     clocks = <&clk81>;
+     clocks = <&clkc CLKID_CLK81>;
 };

Hi Jerome,

Quoted 10 lines · Jerome Brunet

Quoted 5 lines · Martin Blumenstingl

This removes the dummy clk81 gate and replaces it with the actual clock controller's CLKID_CLK81. This will also allow us to pass the real clock IDs to all devices where the clock is controlled by clkc in the future.

Signed-off-by Martin Blumenstingl <[email protected]>

This is going in the right direction and at least align meson8 and meson8b.

Acked-by Jerome Brunet <[email protected]>

that was quick, thanks!

Quoted 2 lines

Later on, I'm wondering if some of these clock assignments should be moved to meson.dtsi ? meson8.dtsi and meson8b.dtsi look very similar

actually I think that the Meson6/MX/<however it is called> clock controller is different (based on a quick look).
so we may end up with a similar situation that we have on GXBB/GXL/GXM: the clock controller will stay in the corresponding .dtsi and we have to "duplicate" the clock assignments for each SoC

however, I guess at some point we can create a .dtsi with all the bits that are shared between Meson8 and Meson8b (during my experiments meson8m2.dtsi just inherits meson8.dtsi and overrides a bunch of compatibles). we can discuss whether we want to move the clock controller to that shared/common .dtsi as well once we start generalizing this

Quoted 97 lines

Quoted 96 lines

---
 arch/arm/boot/dts/meson8.dtsi | 32 ++++++++++++++++----------------
 1 file changed, 16 insertions(+), 16 deletions(-)

arch/arm/boot/dts/meson8.dtsi +16 -16

index 6993077331c7..9b0b3ddbb17e 100644
@@ -43,6 +43,7 @@
  *     OTHER DEALINGS IN THE SOFTWARE.
  */
 
+#include <dt-bindings/clock/meson8b-clkc.h>
 #include <dt-bindings/gpio/meson8-gpio.h>
 /include/ "meson.dtsi"
 

@@ -82,13 +83,6 @@
                      reg = <0x203>;
              };
      };
-
-     clk81: clk at 0 {
-             #clock-cells = <0>;
-             compatible = "fixed-clock";
-             clock-frequency = <141666666>;
-     };
-
 }; /* end of / */
 
 &aobus {

@@ -126,6 +120,12 @@
 };
 
 &cbus {
+     clkc: clock-controller at 4000 {
+             #clock-cells = <1>;
+             compatible = "amlogic,meson8-clkc";
+             reg = <0x8000 0x4>, <0x4000 0x460>;
+     };
+
      pinctrl_cbus: pinctrl at 9880 {
              compatible = "amlogic,meson8-cbus-pinctrl";
              reg = <0x9880 0x10>;

@@ -172,20 +172,20 @@
 };
 
 &ethmac {
-     clocks = <&clk81>;
+     clocks = <&clkc CLKID_CLK81>;
      clock-names = "stmmaceth";
 };
 
 &i2c_AO {
-     clocks = <&clk81>;
+     clocks = <&clkc CLKID_CLK81>;
 };
 
 &i2c_A {
-     clocks = <&clk81>;
+     clocks = <&clkc CLKID_CLK81>;
 };
 
 &i2c_B {
-     clocks = <&clk81>;
+     clocks = <&clkc CLKID_CLK81>;
 };
 
 &L2 {

@@ -195,21 +195,21 @@
 };
 
 &spifc {
-     clocks = <&clk81>;
+     clocks = <&clkc CLKID_CLK81>;
 };
 
 &uart_AO {
-     clocks = <&clk81>;
+     clocks = <&clkc CLKID_CLK81>;
 };
 
 &uart_A {
-     clocks = <&clk81>;
+     clocks = <&clkc CLKID_CLK81>;
 };
 
 &uart_B {
-     clocks = <&clk81>;
+     clocks = <&clkc CLKID_CLK81>;
 };
 
 &uart_C {
-     clocks = <&clk81>;
+     clocks = <&clkc CLKID_CLK81>;
 };

Quoted 5 lines · Martin Blumenstingl

This removes the dummy clk81 gate and replaces it with the actual clock controller's CLKID_CLK81. This will also allow us to pass the real clock IDs to all devices where the clock is controlled by clkc in the future.

Signed-off-by Martin Blumenstingl <[email protected]>

This is going in the right direction and at least align meson8 and meson8b.

Acked-by Jerome Brunet <[email protected]>