minor GXL and GXM improvements
Subsystems (2)
Martin Blumenstingl
reviewercover minor GXL and GXM improvements
This series adds SCPI support to GXL and GXM SoCs by moving the nodes to meson-gx.dtsi. Additionally this updates the compatible string to match the recent changes, see [0]
Now that we have SCPI support for GXM we can also use it to configure the CPU cores using the SCPI DVFS clocks.
[0] http://lists.infradead.org/pipermail/linux-amlogic/2016-November/001632.html
Martin Blumenstingl (2):
ARM64: dts: meson-gx: move the SCPI and SRAM nodes to meson-gx
ARM64: dts: meson-gxm: add SCPI configuration for GXM
arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 45 +++++++++++++++++++++++ arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 57 ----------------------------- arch/arm64/boot/dts/amlogic/meson-gxm.dtsi | 9 +++++ 3 files changed, 54 insertions(+), 57 deletions(-)
Signature · 1 line
2.10.2
Martin Blumenstingl
reviewerPATCH 1/2 ARM64: dts: meson-gx: move the SCPI and SRAM nodes to meson-gx
SCPI and SRAM are identical on GXBB and GXL. Moving the corresponding nodes to meson-gx adds support for the thermal sensor on GXL based devices.
While here, also rename the second compatible string because "arm,legacy-scpi" was replaced by "arm,scpi-pre-1.0".
--- arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 45 +++++++++++++++++++++++ arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 57 ----------------------------- 2 files changed, 45 insertions(+), 57 deletions(-)
arch/arm64/boot/dts/amlogic/meson-gx.dtsi +45 -0
@@ -65,6 +65,7 @@ reg = <0x0 0x0>; enable-method = "psci"; next-level-cache = <&l2>; + clocks = <&scpi_dvfs 0>; }; cpu1: cpu at 1 {
@@ -73,6 +74,7 @@ reg = <0x0 0x1>; enable-method = "psci"; next-level-cache = <&l2>; + clocks = <&scpi_dvfs 0>; }; cpu2: cpu at 2 {
@@ -81,6 +83,7 @@ reg = <0x0 0x2>; enable-method = "psci"; next-level-cache = <&l2>; + clocks = <&scpi_dvfs 0>; }; cpu3: cpu at 3 {
@@ -89,6 +92,7 @@ reg = <0x0 0x3>; enable-method = "psci"; next-level-cache = <&l2>; + clocks = <&scpi_dvfs 0>; }; l2: l2-cache0 {
@@ -153,6 +157,28 @@ }; }; + scpi { + compatible = "amlogic,meson-gxbb-scpi", "arm,scpi-pre-1.0"; + mboxes = <&mailbox 1 &mailbox 2>; + shmem = <&cpu_scp_lpri &cpu_scp_hpri>; + + clocks { + compatible = "arm,scpi-clocks"; + + scpi_dvfs: scpi_clocks at 0 { + compatible = "arm,scpi-dvfs-clocks"; + #clock-cells = <1>; + clock-indices = <0>; + clock-output-names = "vcpu"; + }; + }; + + scpi_sensors: sensors { + compatible = "arm,scpi-sensors"; + #thermal-sensor-cells = <1>; + }; + }; + soc { compatible = "simple-bus"; #address-cells = <2>;
@@ -264,6 +290,25 @@ #address-cells = <0>; }; + sram: sram at c8000000 { + compatible = "amlogic,meson-gxbb-sram", "mmio-sram"; + reg = <0x0 0xc8000000 0x0 0x14000>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0 0xc8000000 0x14000>; + + cpu_scp_lpri: scp-shmem at 0 { + compatible = "amlogic,meson-gxbb-scp-shmem"; + reg = <0x13000 0x400>; + }; + + cpu_scp_hpri: scp-shmem at 200 { + compatible = "amlogic,meson-gxbb-scp-shmem"; + reg = <0x13400 0x400>; + }; + }; + aobus: aobus at c8100000 { compatible = "simple-bus"; reg = <0x0 0xc8100000 0x0 0x100000>;
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi +0 -57
75 lines not on this page · raw message
Signature · 1 line
2.10.2
PATCH 1/2 ARM64: dts: meson-gx: move the SCPI and SRAM nodes to meson-gx
Quoted 176 lines · Martin Blumenstingl
SCPI and SRAM are identical on GXBB and GXL. Moving the corresponding nodes to meson-gx adds support for the thermal sensor on GXL based devices.
While here, also rename the second compatible string because "arm,legacy-scpi" was replaced by "arm,scpi-pre-1.0".Signed-off-by Martin Blumenstingl <[email protected]>--- arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 45 +++++++++++++++++++++++ arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 57 ----------------------------- 2 files changed, 45 insertions(+), 57 deletions(-)arch/arm64/boot/dts/amlogic/meson-gx.dtsi +45
-0@@ -65,6 +65,7 @@ reg = <0x0 0x0>; enable-method = "psci"; next-level-cache = <&l2>; + clocks = <&scpi_dvfs 0>; }; cpu1: cpu at 1 {@@ -73,6 +74,7 @@ reg = <0x0 0x1>; enable-method = "psci"; next-level-cache = <&l2>; + clocks = <&scpi_dvfs 0>; }; cpu2: cpu at 2 {@@ -81,6 +83,7 @@ reg = <0x0 0x2>; enable-method = "psci"; next-level-cache = <&l2>; + clocks = <&scpi_dvfs 0>; }; cpu3: cpu at 3 {@@ -89,6 +92,7 @@ reg = <0x0 0x3>; enable-method = "psci"; next-level-cache = <&l2>; + clocks = <&scpi_dvfs 0>; }; l2: l2-cache0 {@@ -153,6 +157,28 @@ }; }; + scpi { + compatible = "amlogic,meson-gxbb-scpi", "arm,scpi-pre-1.0"; + mboxes = <&mailbox 1 &mailbox 2>; + shmem = <&cpu_scp_lpri &cpu_scp_hpri>; + + clocks { + compatible = "arm,scpi-clocks"; + + scpi_dvfs: scpi_clocks at 0 { + compatible = "arm,scpi-dvfs-clocks"; + #clock-cells = <1>; + clock-indices = <0>; + clock-output-names = "vcpu"; + }; + }; + + scpi_sensors: sensors { + compatible = "arm,scpi-sensors"; + #thermal-sensor-cells = <1>; + }; + }; + soc { compatible = "simple-bus"; #address-cells = <2>;@@ -264,6 +290,25 @@ #address-cells = <0>; }; + sram: sram at c8000000 { + compatible = "amlogic,meson-gxbb-sram", "mmio-sram"; + reg = <0x0 0xc8000000 0x0 0x14000>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0 0xc8000000 0x14000>; + + cpu_scp_lpri: scp-shmem at 0 { + compatible = "amlogic,meson-gxbb-scp-shmem"; + reg = <0x13000 0x400>; + }; + + cpu_scp_hpri: scp-shmem at 200 { + compatible = "amlogic,meson-gxbb-scp-shmem"; + reg = <0x13400 0x400>; + }; + }; + aobus: aobus at c8100000 { compatible = "simple-bus"; reg = <0x0 0xc8100000 0x0 0x100000>;arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi +0
-50@@ -50,28 +50,6 @@ / { compatible = "amlogic,meson-gxbb"; - scpi { - compatible = "amlogic,meson-gxbb-scpi"; - mboxes = <&mailbox 1 &mailbox 2>; - shmem = <&cpu_scp_lpri &cpu_scp_hpri>; - - clocks { - compatible = "arm,scpi-clocks"; - - scpi_dvfs: scpi_clocks at 0 { - compatible = "arm,scpi-dvfs-clocks"; - #clock-cells = <1>; - clock-indices = <0>; - clock-output-names = "vcpu"; - }; - }; - - scpi_sensors: sensors { - compatible = "arm,scpi-sensors"; - #thermal-sensor-cells = <1>; - }; - }; - soc { usb0_phy: phy at c0000000 { compatible = "amlogic,meson-gxbb-usb2-phy";@@ -93,25 +71,6 @@ status = "disabled"; }; - sram: sram at c8000000 { - compatible = "amlogic,meson-gxbb-sram", "mmio-sram"; - reg = <0x0 0xc8000000 0x0 0x14000>; - - #address-cells = <1>; - #size-cells = <1>; - ranges = <0 0x0 0xc8000000 0x14000>; - - cpu_scp_lpri: scp-shmem at 0 { - compatible = "amlogic,meson-gxbb-scp-shmem"; - reg = <0x13000 0x400>; - }; - - cpu_scp_hpri: scp-shmem at 200 { - compatible = "amlogic,meson-gxbb-scp-shmem"; - reg = <0x13400 0x400>; - }; - }; - usb0: usb at c9000000 { compatible = "amlogic,meson-gxbb-usb", "snps,dwc2"; reg = <0x0 0xc9000000 0x0 0x40000>;@@ -138,22 +97,6 @@ }; }; -&cpu0 { - clocks = <&scpi_dvfs 0>; -}; - -&cpu1 { - clocks = <&scpi_dvfs 0>; -}; - -&cpu2 {
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi line 102
Quoted 10 lines
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi +0
-7- clocks = <&scpi_dvfs 0>; -}; - -&cpu3 { - clocks = <&scpi_dvfs 0>; -}; - &cbus { spifc: spi at 8c80 { compatible = "amlogic,meson-gxbb-spifc";
Tested successfully on my P200 (S905) and Nexbox A95X (S905X)
So
Martin Blumenstingl
reviewerPATCH 2/2 ARM64: dts: meson-gxm: add SCPI configuration for GXM
In reply to Martin BlumenstinglThis adds the SCPI DVFS clock index and configures the CPU cores accordingly.
--- arch/arm64/boot/dts/amlogic/meson-gxm.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+)
arch/arm64/boot/dts/amlogic/meson-gxm.dtsi +9 -0
@@ -85,6 +85,7 @@ reg = <0x0 0x100>; enable-method = "psci"; next-level-cache = <&l2>; + clocks = <&scpi_dvfs 1>; }; cpu5: cpu at 101 {
@@ -93,6 +94,7 @@ reg = <0x0 0x101>; enable-method = "psci"; next-level-cache = <&l2>; + clocks = <&scpi_dvfs 1>; }; cpu6: cpu at 102 {
@@ -101,6 +103,7 @@ reg = <0x0 0x102>; enable-method = "psci"; next-level-cache = <&l2>; + clocks = <&scpi_dvfs 1>; }; cpu7: cpu at 103 {
@@ -109,6 +112,12 @@ reg = <0x0 0x103>; enable-method = "psci"; next-level-cache = <&l2>; + clocks = <&scpi_dvfs 1>; }; }; }; + +&scpi_dvfs { + clock-indices = <0 1>; + clock-output-names = "vbig", "vlittle"; +};
Signature · 1 line
2.10.2
PATCH 2/2 ARM64: dts: meson-gxm: add SCPI configuration for GXM
Quoted 40 lines · Martin Blumenstingl
This adds the SCPI DVFS clock index and configures the CPU cores accordingly.
Signed-off-by Martin Blumenstingl <[email protected]>--- arch/arm64/boot/dts/amlogic/meson-gxm.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+)arch/arm64/boot/dts/amlogic/meson-gxm.dtsi +3
-0@@ -85,6 +85,7 @@ reg = <0x0 0x100>; enable-method = "psci"; next-level-cache = <&l2>; + clocks = <&scpi_dvfs 1>; }; cpu5: cpu at 101 {@@ -93,6 +94,7 @@ reg = <0x0 0x101>; enable-method = "psci"; next-level-cache = <&l2>; + clocks = <&scpi_dvfs 1>; }; cpu6: cpu at 102 {@@ -101,6 +103,7 @@ reg = <0x0 0x102>; enable-method = "psci"; next-level-cache = <&l2>; + clocks = <&scpi_dvfs 1>; }; cpu7: cpu at 103 {@@ -109,6 +112,12 @@ reg = <0x0 0x103>; enable-method = "psci";
arch/arm64/boot/dts/amlogic/meson-gxm.dtsi line 123
Quoted 10 lines
arch/arm64/boot/dts/amlogic/meson-gxm.dtsi +6
-0next-level-cache = <&l2>; + clocks = <&scpi_dvfs 1>; }; }; }; + +&scpi_dvfs { + clock-indices = <0 1>; + clock-output-names = "vbig", "vlittle"; +};
Tested successfully on my Nexbox A1 (S912)
So
Kevin Hilman
maintainercover minor GXL and GXM improvements
In reply to Martin BlumenstinglHi Martin,
Quoted 3 lines · Martin Blumenstingl
This series adds SCPI support to GXL and GXM SoCs by moving the nodes to
meson-gx.dtsi. Additionally this updates the compatible string to match the recent changes, see [0]
Can you rebase onto my current v4.10/dt64 branch please? I have updated the compatible string there.
Thanks,
Kevin
Martin Blumenstingl
reviewerv2 cover GXL and GXM SCPI improvements
In reply to Martin BlumenstinglThis series adds SCPI support to GXL and GXM SoCs by moving the nodes to meson-gx.dtsi.
Now that we have SCPI support for GXM we can also use it to configure the CPU cores using the SCPI DVFS clocks.
Changes since v1:
- added Tested-By and Acked-By tags from Neil Armstrong (thanks!)
- rebased to khilman/linux-amlogic.git/amlogic-dt64-2-v2
- updated description of patch 1 because the "arm,scpi-pre-1.0" change is already part of the amlogic-dt64-2-v2 tag
Martin Blumenstingl (2):
ARM64: dts: meson-gx: move the SCPI and SRAM nodes to meson-gx
ARM64: dts: meson-gxm: add SCPI configuration for GXM
arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 45 +++++++++++++++++++++++ arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 57 ----------------------------- arch/arm64/boot/dts/amlogic/meson-gxm.dtsi | 9 +++++ 3 files changed, 54 insertions(+), 57 deletions(-)
Signature · 1 line
2.10.2
Martin Blumenstingl
reviewerPATCH v2 1/2 ARM64: dts: meson-gx: move the SCPI and SRAM nodes to meson-gx
SCPI and SRAM are identical on GXBB and GXL. Moving the corresponding nodes to meson-gx adds support for the thermal sensor on GXL based devices.
--- arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 45 +++++++++++++++++++++++ arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 57 ----------------------------- 2 files changed, 45 insertions(+), 57 deletions(-)
arch/arm64/boot/dts/amlogic/meson-gx.dtsi +45 -0
@@ -65,6 +65,7 @@ reg = <0x0 0x0>; enable-method = "psci"; next-level-cache = <&l2>; + clocks = <&scpi_dvfs 0>; }; cpu1: cpu at 1 {
@@ -73,6 +74,7 @@ reg = <0x0 0x1>; enable-method = "psci"; next-level-cache = <&l2>; + clocks = <&scpi_dvfs 0>; }; cpu2: cpu at 2 {
@@ -81,6 +83,7 @@ reg = <0x0 0x2>; enable-method = "psci"; next-level-cache = <&l2>; + clocks = <&scpi_dvfs 0>; }; cpu3: cpu at 3 {
@@ -89,6 +92,7 @@ reg = <0x0 0x3>; enable-method = "psci"; next-level-cache = <&l2>; + clocks = <&scpi_dvfs 0>; }; l2: l2-cache0 {
@@ -153,6 +157,28 @@ }; }; + scpi { + compatible = "amlogic,meson-gxbb-scpi", "arm,scpi-pre-1.0"; + mboxes = <&mailbox 1 &mailbox 2>; + shmem = <&cpu_scp_lpri &cpu_scp_hpri>; + + clocks { + compatible = "arm,scpi-clocks"; + + scpi_dvfs: scpi_clocks at 0 { + compatible = "arm,scpi-dvfs-clocks"; + #clock-cells = <1>; + clock-indices = <0>; + clock-output-names = "vcpu"; + }; + }; + + scpi_sensors: sensors { + compatible = "arm,scpi-sensors"; + #thermal-sensor-cells = <1>; + }; + }; + soc { compatible = "simple-bus"; #address-cells = <2>;
@@ -264,6 +290,25 @@ #address-cells = <0>; }; + sram: sram at c8000000 { + compatible = "amlogic,meson-gxbb-sram", "mmio-sram"; + reg = <0x0 0xc8000000 0x0 0x14000>; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0 0xc8000000 0x14000>; + + cpu_scp_lpri: scp-shmem at 0 { + compatible = "amlogic,meson-gxbb-scp-shmem"; + reg = <0x13000 0x400>; + }; + + cpu_scp_hpri: scp-shmem at 200 { + compatible = "amlogic,meson-gxbb-scp-shmem"; + reg = <0x13400 0x400>; + }; + }; + aobus: aobus at c8100000 { compatible = "simple-bus"; reg = <0x0 0xc8100000 0x0 0x100000>;
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi +0 -57
75 lines not on this page · raw message
Signature · 1 line
2.10.2
Martin Blumenstingl
reviewerPATCH v2 2/2 ARM64: dts: meson-gxm: add SCPI configuration for GXM
In reply to Martin BlumenstinglThis adds the SCPI DVFS clock index and configures the CPU cores accordingly.
--- arch/arm64/boot/dts/amlogic/meson-gxm.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+)
arch/arm64/boot/dts/amlogic/meson-gxm.dtsi +9 -0
@@ -85,6 +85,7 @@ reg = <0x0 0x100>; enable-method = "psci"; next-level-cache = <&l2>; + clocks = <&scpi_dvfs 1>; }; cpu5: cpu at 101 {
@@ -93,6 +94,7 @@ reg = <0x0 0x101>; enable-method = "psci"; next-level-cache = <&l2>; + clocks = <&scpi_dvfs 1>; }; cpu6: cpu at 102 {
@@ -101,6 +103,7 @@ reg = <0x0 0x102>; enable-method = "psci"; next-level-cache = <&l2>; + clocks = <&scpi_dvfs 1>; }; cpu7: cpu at 103 {
@@ -109,6 +112,12 @@ reg = <0x0 0x103>; enable-method = "psci"; next-level-cache = <&l2>; + clocks = <&scpi_dvfs 1>; }; }; }; + +&scpi_dvfs { + clock-indices = <0 1>; + clock-output-names = "vbig", "vlittle"; +};
Signature · 1 line
2.10.2
Kevin Hilman
maintainerv2 cover GXL and GXM SCPI improvements
In reply to Martin BlumenstinglQuoted 10 lines · Martin Blumenstingl
This series adds SCPI support to GXL and GXM SoCs by moving the nodes to
meson-gx.dtsi.
Now that we have SCPI support for GXM we can also use it to configure the CPU cores using the SCPI DVFS clocks.Changes since v1:
- added Tested-By and Acked-By tags from Neil Armstrong (thanks!)
- rebased to khilman/linux-amlogic.git/amlogic-dt64-2-v2
- updated description of patch 1 because the "arm,scpi-pre-1.0" change is already part of the amlogic-dt64-2-v2 tag
Thanks for the respin. It's now too late for v4.10 (I freeze things around -rc6 or -rc7, and it's now -rc8), but I'll queue this up for v4.11.
Thanks,
Kevin