Add support for AmLogic GXBB clock controller
Subsystems (5)
cover Add support for AmLogic GXBB clock controller
This series is based on the AmLogic Meson8b rewrite/cleanup[0]. The AmLogic GXBB is an ARMv8-based SoC, fed by a 24MHZ xtal, and it provides several PLLs, muxes dividers and gates to drive CPUs and peripherals.
While based on the Meson8b clock controller driver, this series adds supports for Multi-phase Locked Loops (mpll) and support for PLLs with fractional rates.
This series introduces the clock controller driver for the gxbb, including the DT binding description and accompanying change in the gxbb dtsi. Only three clocks are exposed via the headers in the dt-bindings include-chroot. More can be added later, but since these values represent an ABI I wanted to start small. I'm not sure about the names for the gate clocks, so I especially tried to avoid putting those in the binding (with the exception of the Ethernet gate, which Kevin has needed for a while).
Notably missing from this driver are the branch clocks (e.g. the mess of muxes and dividers that come after the PLLs and MPLLs). I could have guessed how things were wired up from the resources available to me, but I'm hoping to get some improved documentation soon and then I'll go back and fill them in.
[0] http://lkml.kernel.org/g/1465518467-23939-1-git-send-email-mturquette at baylibre.com
Michael Turquette (7):
clk: meson: add peripheral gate macro
clk: meson: add mpll support
clk: meson: fractional pll support
clk: gxbb: Document bindings for the GXBB clock controller
clk: gxbb: add AmLogic GXBB clk controller driver
arm64: amlogic: select gxbb clk driver
arm64: dts: gxbb clock controller
.../bindings/clock/amlogic,gxbb-clkc.txt | 36 + arch/arm64/Kconfig.platforms | 2 + arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 7 + drivers/clk/meson/Kconfig | 7 + drivers/clk/meson/Makefile | 3 +- drivers/clk/meson/clk-mpll.c | 94 ++ drivers/clk/meson/clk-pll.c | 32 +- drivers/clk/meson/clkc.h | 39 + drivers/clk/meson/gxbb.c | 954 +++++++++++++++++++++ drivers/clk/meson/gxbb.h | 271 ++++++ include/dt-bindings/clock/gxbb-clkc.h | 12 + 11 files changed, 1454 insertions(+), 3 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt create mode 100644 drivers/clk/meson/clk-mpll.c create mode 100644 drivers/clk/meson/gxbb.c create mode 100644 drivers/clk/meson/gxbb.h create mode 100644 include/dt-bindings/clock/gxbb-clkc.h
Signature · 1 line
2.1.4
PATCH 1/7 clk: meson: add peripheral gate macro
There are a series of peripheral and system gate clocks that fan out from the clk81 signal. Add a helper macro to statically initialize these gate clocks.
--- drivers/clk/meson/clkc.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+)
drivers/clk/meson/clkc.h +14 -0
@@ -73,6 +73,20 @@ struct meson_clk_cpu {int meson_clk_cpu_notifier_cb (struct notifier_block *nb,unsigned long event,void *data); +#define MESON_GATE (_name, _reg, _bit) \ +struct clk_gate gxbb_##_name = { \ + .reg = (void __iomem *) _reg, \ + .bit_idx = (_bit), \ + .lock = &clk_lock, \ + .hw.init = &(struct clk_init_data) { \ + .name = #_name, \ + .ops = &clk_gate_ops, \ + .parent_names = (const char *[]){ "clk81" }, \ + .num_parents = 1, \ + .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED), \ + }, \ +}; +/* clk_ops */ extern const struct clk_ops meson_clk_pll_ro_ops;extern const struct clk_ops meson_clk_pll_ops;
Signature · 1 line
2.1.4
PATCH 2/7 clk: meson: add mpll support
In reply to Michael TurquetteMPLLs are adjustable rate clocks derived from PLLs. On both Meson8b and GXBB they appear to be only derived from fixed_pll.
Add support for these clock types so that they can be added to their respective drivers.
--- drivers/clk/meson/Makefile | 2 +- drivers/clk/meson/clk-mpll.c | 94 ++++++++++++++++++++++++++++++++++++++++++++ drivers/clk/meson/clkc.h | 10 +++++ 3 files changed, 105 insertions(+), 1 deletion(-) create mode 100644 drivers/clk/meson/clk-mpll.c
drivers/clk/meson/Makefile +1 -1
@@ -2,5 +2,5 @@ # Makefile for Meson specific clk # -obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-cpu.o +obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-cpu.o clk-mpll.o obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b-clkc.o
drivers/clk/meson/clk-mpll.c new file +94 -0
94 lines not on this page · raw message
drivers/clk/meson/clkc.h +10 -0
@@ -73,6 +73,15 @@ struct meson_clk_cpu {int meson_clk_cpu_notifier_cb (struct notifier_block *nb,unsigned long event,void *data); +struct meson_clk_mpll { +struct clk_hw hw; +void __iomem *base; +struct parm sdm; +struct parm n2; +/* FIXME ssen gate control? */ +spinlock_t *lock; +}; +#define MESON_GATE (_name, _reg, _bit) \ struct clk_gate gxbb_##_name = { \ .reg = (void __iomem *) _reg, \
@@ -91,5 +100,6 @@ struct clk_gate gxbb_##_name = { \extern const struct clk_ops meson_clk_pll_ro_ops;extern const struct clk_ops meson_clk_pll_ops;extern const struct clk_ops meson_clk_cpu_ops; +extern const struct clk_ops meson_clk_mpll_ro_ops;#endif /* __CLKC_H */
Signature · 1 line
2.1.4
PATCH 3/7 clk: meson: fractional pll support
In reply to Michael Turquette--- drivers/clk/meson/clk-pll.c | 32 ++++++++++++++++++++++++++++++-- drivers/clk/meson/clkc.h | 15 +++++++++++++++ 2 files changed, 45 insertions(+), 2 deletions(-)
drivers/clk/meson/clk-pll.c +30 -2
@@ -53,7 +53,7 @@ static unsigned long meson_clk_pll_recalc_rate(struct clk_hw *hw,struct parm *p;unsigned long parent_rate_mhz = parent_rate /1000000 ;unsigned long rate_mhz; -u16 n, m, od; +u16 n, m, frac =0 , od, od2 =0 ;u32 reg; p = &pll->n;
@@ -68,7 +68,21 @@ static unsigned long meson_clk_pll_recalc_rate(struct clk_hw *hw, reg =readl (pll->base + p->reg_off); od =PARM_GET (p->width, p->shift, reg); - rate_mhz = (parent_rate_mhz * m / n) >> od; + p = &pll->od2; +if (p->width) { + reg =readl (pll->base + p->reg_off); + od2 =PARM_GET (p->width, p->shift, reg); + } + + p = &pll->frac; +if (p->width) { + reg =readl (pll->base + p->reg_off); + frac =PARM_GET (p->width, p->shift, reg); + rate_mhz = (parent_rate_mhz * m + \ + (parent_rate_mhz * frac >>12 )) *2 / n; + rate_mhz = rate_mhz >> od >> od2; + }else + rate_mhz = (parent_rate_mhz * m / n) >> od >> od2;return rate_mhz *1000000 ; }
@@ -155,6 +169,20 @@ static int meson_clk_pll_set_rate(struct clk_hw *hw, unsigned long rate, reg =PARM_SET (p->width, p->shift, reg, rate_set->od);writel (reg, pll->base + p->reg_off); + p = &pll->od2; +if (p->width) { + reg =readl (pll->base + p->reg_off); + reg =PARM_SET (p->width, p->shift, reg, rate_set->od2); +writel (reg, pll->base + p->reg_off); + } + + p = &pll->frac; +if (p->width) { + reg =readl (pll->base + p->reg_off); + reg =PARM_SET (p->width, p->shift, reg, rate_set->frac); +writel (reg, pll->base + p->reg_off); + } + p = &pll->n; ret =meson_clk_pll_wait_lock (pll, p);if (ret) {
drivers/clk/meson/clkc.h +15 -0
@@ -40,7 +40,10 @@ struct pll_rate_table {u16 m;u16 n;u16 od; +u16 od2; +u16 frac; }; +#define PLL_RATE (_r, _m, _n, _od) \ { \ .rate = (_r), \
@@ -49,12 +52,24 @@ struct pll_rate_table { .od = (_od), \ } \ +#define PLL_FRAC_RATE (_r, _m, _n, _od, _od2, _frac) \ + { \ + .rate = (_r), \ + .m = (_m), \ + .n = (_n), \ + .od = (_od), \ + .od2 = (_od2), \ + .frac = (_frac), \ + } \ +struct meson_clk_pll {struct clk_hw hw;void __iomem *base;struct parm m;struct parm n; +struct parm frac;struct parm od; +struct parm od2;const struct pll_rate_table *rate_table;unsigned int rate_count;spinlock_t *lock;
Signature · 1 line
2.1.4
PATCH 4/7 clk: gxbb: Document bindings for the GXBB clock controller
In reply to Michael TurquetteAdd documentations for the clock controller.
--- .../bindings/clock/amlogic,gxbb-clkc.txt | 36 ++++++++++++++++++++++ 1 file changed, 36 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt
Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt new file +36 -0
@@ -0,0 +1,36 @@ +* Amlogic GXBB Clock and Reset Unit + +The Amlogic GXBB clock controller generates and supplies clock to various +controllers within the SoC. + +Required Properties: + +- compatible: should be "amlogic,gxbb-clkc" +- reg: physical base address of the clock controller and length of memory + mapped region. + +- #clock-cells: should be 1. + +Each clock is assigned an identifier and client nodes can use this identifier +to specify the clock which they consume. All available clocks are defined as +preprocessor macros in the dt-bindings/clock/gxbb-clkc.h header and can be +used in device tree sources. + +Example: Clock controller node: + + clkc: clock-controller at c883c000 { + #clock-cells = <1>; + compatible = "amlogic,gxbb-clkc"; + reg = <0x0 0xc883c000 0x0 0x3db>; + }; + +Example: UART controller node that consumes the clock generated by the clock + controller: + + uart_AO: serial at c81004c0 { + compatible = "amlogic,meson-uart"; + reg = <0xc81004c0 0x14>; + interrupts = <0 90 1>; + clocks = <&clkc CLKID_CLK81>; + status = "disabled"; + };
Signature · 1 line
2.1.4
PATCH 5/7 clk: gxbb: add AmLogic GXBB clk controller driver
In reply to Michael Turquette--- drivers/clk/meson/Kconfig | 7 + drivers/clk/meson/Makefile | 1 + drivers/clk/meson/gxbb.c | 954 ++++++++++++++++++++++++++++++++++ drivers/clk/meson/gxbb.h | 271 ++++++++++ include/dt-bindings/clock/gxbb-clkc.h | 12 + 5 files changed, 1245 insertions(+) create mode 100644 drivers/clk/meson/gxbb.c create mode 100644 drivers/clk/meson/gxbb.h create mode 100644 include/dt-bindings/clock/gxbb-clkc.h
drivers/clk/meson/Kconfig +7 -0
@@ -10,3 +10,10 @@ config COMMON_CLK_MESON8B Support for the clock controller on AmLogic S805 devices, aka meson8b. Say Y if you want peripherals and CPU frequency scaling to work. + +config COMMON_CLK_GXBB + bool + depends on COMMON_CLK_AMLOGIC + help + Support for the clock controller on AmLogic S905 devices, aka gxbb. + Say Y if you want peripherals and CPU frequency scaling to work.
drivers/clk/meson/Makefile +1 -0
@@ -4,3 +4,4 @@ obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-cpu.o clk-mpll.o obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b-clkc.o +obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o
drivers/clk/meson/gxbb.c new file +954 -0
954 lines not on this page · raw message
drivers/clk/meson/gxbb.h new file +271 -0
271 lines not on this page · raw message
include/dt-bindings/clock/gxbb-clkc.h new file +12 -0
@@ -0,0 +1,12 @@ +/* +* GXBB clock tree IDs +*/ + +#ifndef __GXBB_CLKC_H +#define __GXBB_CLKC_H + +#define CLKID_CPUCLK 1 +#define CLKID_CLK81 12 +#define CLKID_ETH 36 + +#endif /* __GXBB_CLKC_H */
Signature · 1 line
2.1.4
PATCH 6/7 arm64: amlogic: select gxbb clk driver
In reply to Michael TurquetteThe AmLogic clock controller code is used by both arm and arm64 architectures. Explicitly select the core code for all Meson (arm64) builds, and also select the GXBB driver, since that's the way arm64 does things.
--- arch/arm64/Kconfig.platforms | 2 ++ 1 file changed, 2 insertions(+)
arch/arm64/Kconfig.platforms +2 -0
@@ -66,6 +66,8 @@ config ARCH_MEDIATEK config ARCH_MESON bool "Amlogic Platforms" + select COMMON_CLK_AMLOGIC + select COMMON_CLK_GXBB help This enables support for the Amlogic S905 SoCs.
Signature · 1 line
2.1.4
PATCH 7/7 arm64: dts: gxbb clock controller
In reply to Michael TurquetteAdd the clock controller node for the AmLogic GXBB machine.
--- arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 7 +++++++ 1 file changed, 7 insertions(+)
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi +7 -0
@@ -174,5 +174,12 @@ #size-cells = <2>; ranges = <0x0 0x0 0x0 0xd0000000 0x0 0x200000>; }; + + clkc: clock-controller at c883c000 { + compatible = "amlogic,gxbb-clkc"; + #clock-cells = <1>; + reg = <0x0 0xc883c000 0x0 0x3db>; + }; + }; };
Signature · 1 line
2.1.4
Kevin Hilman
maintainerPATCH 7/7 arm64: dts: gxbb clock controller
Quoted 14 lines · Michael Turquette
Add the clock controller node for the AmLogic GXBB machine.
Signed-off-by Michael Turquette <[email protected]>--- arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 7 +++++++ 1 file changed, 7 insertions(+)arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi +0
-0@@ -174,5 +174,12 @@ #size-cells = <2>; ranges = <0x0 0x0 0x0 0xd0000000 0x0 0x200000>;
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi line 185
Quoted 10 lines
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi +7
-0}; + + clkc: clock-controller at c883c000 { + compatible = "amlogic,gxbb-clkc"; + #clock-cells = <1>; + reg = <0x0 0xc883c000 0x0 0x3db>; + }; + }; };
minor nit: could you put this under the (recently added) hibus node (at offset 0). See the DT in my for-next branch for reference:
https://git.kernel.org/cgit/linux/kernel/git/khilman/linux-amlogic.git/log/?h=for-next
Thanks,
Kevin
PATCH 7/7 arm64: dts: gxbb clock controller
Quoting Kevin Hilman (2016-06-14 12:01:26)
Quoted 21 lines
Quoted 19 lines · Michael Turquette
Add the clock controller node for the AmLogic GXBB machine.
Signed-off-by Michael Turquette <[email protected]>--- arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 7 +++++++ 1 file changed, 7 insertions(+)arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi +4
-0@@ -174,5 +174,12 @@ #size-cells = <2>; ranges = <0x0 0x0 0x0 0xd0000000 0x0 0x200000>; }; + + clkc: clock-controller at c883c000 { + compatible = "amlogic,gxbb-clkc"; + #clock-cells = <1>;
Quoted 8 lines
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi line 185
Quoted 5 lines
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi +3
-0+ reg = <0x0 0xc883c000 0x0 0x3db>; + }; + }; };minor nit: could you put this under the (recently added) hibus node (at offset 0). See the DT in my for-next branch for reference:
Ah, I had wondered about that. Will do.
Thanks for reviewing,
Mike
Quoted 6 lines
https://git.kernel.org/cgit/linux/kernel/git/khilman/linux-amlogic.git/log/?h=for-next
Thanks,
Kevin
cover Add support for AmLogic GXBB clock controller
In reply to Michael TurquetteQuoted 43 lines · Michael Turquette
This series is based on the AmLogic Meson8b rewrite/cleanup[0]. The AmLogic GXBB is an ARMv8-based SoC, fed by a 24MHZ xtal, and it provides several PLLs, muxes dividers and gates to drive CPUs and peripherals.
While based on the Meson8b clock controller driver, this series adds supports for Multi-phase Locked Loops (mpll) and support for PLLs with fractional rates.
This series introduces the clock controller driver for the gxbb, including the DT binding description and accompanying change in the gxbb dtsi. Only three clocks are exposed via the headers in the dt-bindings include-chroot. More can be added later, but since these values represent an ABI I wanted to start small. I'm not sure about the names for the gate clocks, so I especially tried to avoid putting those in the binding (with the exception of the Ethernet gate, which Kevin has needed for a while).
Notably missing from this driver are the branch clocks (e.g. the mess of muxes and dividers that come after the PLLs and MPLLs). I could have guessed how things were wired up from the resources available to me, but I'm hoping to get some improved documentation soon and then I'll go back and fill them in.
[0] http://lkml.kernel.org/g/1465518467-23939-1-git-send-email-mturquette at baylibre.com
Michael Turquette (7):
clk: meson: add peripheral gate macro
clk: meson: add mpll support
clk: meson: fractional pll support
clk: gxbb: Document bindings for the GXBB clock controller
clk: gxbb: add AmLogic GXBB clk controller driver
arm64: amlogic: select gxbb clk driver
arm64: dts: gxbb clock controller.../bindings/clock/amlogic,gxbb-clkc.txt | 36 + arch/arm64/Kconfig.platforms | 2 + arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 7 + drivers/clk/meson/Kconfig | 7 + drivers/clk/meson/Makefile | 3 +- drivers/clk/meson/clk-mpll.c | 94 ++ drivers/clk/meson/clk-pll.c | 32 +- drivers/clk/meson/clkc.h | 39 + drivers/clk/meson/gxbb.c | 954 +++++++++++++++++++++
Quoted 9 lines
drivers/clk/meson/gxbb.h | 271 ++++++ include/dt-bindings/clock/gxbb-clkc.h | 12 + 11 files changed, 1454 insertions(+), 3 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt create mode 100644 drivers/clk/meson/clk-mpll.c create mode 100644 drivers/clk/meson/gxbb.c create mode 100644 drivers/clk/meson/gxbb.h create mode 100644 include/dt-bindings/clock/gxbb-clkc.h
Mike,
I did not receive the 5/7 on the mailing list, can you resend ?
Neil
Kevin Hilman
maintainercover Add support for AmLogic GXBB clock controller
Quoted 54 lines · Neil Armstrong
Quoted 43 lines · Michael Turquette
This series is based on the AmLogic Meson8b rewrite/cleanup[0]. The AmLogic GXBB is an ARMv8-based SoC, fed by a 24MHZ xtal, and it provides several PLLs, muxes dividers and gates to drive CPUs and peripherals.
While based on the Meson8b clock controller driver, this series adds supports for Multi-phase Locked Loops (mpll) and support for PLLs with fractional rates.
This series introduces the clock controller driver for the gxbb, including the DT binding description and accompanying change in the gxbb dtsi. Only three clocks are exposed via the headers in the dt-bindings include-chroot. More can be added later, but since these values represent an ABI I wanted to start small. I'm not sure about the names for the gate clocks, so I especially tried to avoid putting those in the binding (with the exception of the Ethernet gate, which Kevin has needed for a while).
Notably missing from this driver are the branch clocks (e.g. the mess of muxes and dividers that come after the PLLs and MPLLs). I could have guessed how things were wired up from the resources available to me, but I'm hoping to get some improved documentation soon and then I'll go back and fill them in.
[0] http://lkml.kernel.org/g/1465518467-23939-1-git-send-email-mturquette at baylibre.com
Michael Turquette (7):
clk: meson: add peripheral gate macro
clk: meson: add mpll support
clk: meson: fractional pll support
clk: gxbb: Document bindings for the GXBB clock controller
clk: gxbb: add AmLogic GXBB clk controller driver
arm64: amlogic: select gxbb clk driver
arm64: dts: gxbb clock controller.../bindings/clock/amlogic,gxbb-clkc.txt | 36 + arch/arm64/Kconfig.platforms | 2 + arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 7 + drivers/clk/meson/Kconfig | 7 + drivers/clk/meson/Makefile | 3 +- drivers/clk/meson/clk-mpll.c | 94 ++ drivers/clk/meson/clk-pll.c | 32 +- drivers/clk/meson/clkc.h | 39 + drivers/clk/meson/gxbb.c | 954 +++++++++++++++++++++Quoted 9 lines
drivers/clk/meson/gxbb.h | 271 ++++++ include/dt-bindings/clock/gxbb-clkc.h | 12 + 11 files changed, 1454 insertions(+), 3 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt create mode 100644 drivers/clk/meson/clk-mpll.c create mode 100644 drivers/clk/meson/gxbb.c create mode 100644 drivers/clk/meson/gxbb.h create mode 100644 include/dt-bindings/clock/gxbb-clkc.h
Quoted 4 lines
Mike,
I did not receive the 5/7 on the mailing list, can you resend ?
Neil, did you end up receiving this?
The mailing-list had a size limit that caught this one. I bumped it up and approved the mail, so it shold've gone through, and shows in
patchwork: https://patchwork.kernel.org/patch/9170173/
Kevin
cover Add support for AmLogic GXBB clock controller
Quoted 58 lines · Kevin Hilman
Quoted 56 lines · Neil Armstrong
Quoted 43 lines · Michael Turquette
This series is based on the AmLogic Meson8b rewrite/cleanup[0]. The AmLogic GXBB is an ARMv8-based SoC, fed by a 24MHZ xtal, and it provides several PLLs, muxes dividers and gates to drive CPUs and peripherals.
While based on the Meson8b clock controller driver, this series adds supports for Multi-phase Locked Loops (mpll) and support for PLLs with fractional rates.
This series introduces the clock controller driver for the gxbb, including the DT binding description and accompanying change in the gxbb dtsi. Only three clocks are exposed via the headers in the dt-bindings include-chroot. More can be added later, but since these values represent an ABI I wanted to start small. I'm not sure about the names for the gate clocks, so I especially tried to avoid putting those in the binding (with the exception of the Ethernet gate, which Kevin has needed for a while).
Notably missing from this driver are the branch clocks (e.g. the mess of muxes and dividers that come after the PLLs and MPLLs). I could have guessed how things were wired up from the resources available to me, but I'm hoping to get some improved documentation soon and then I'll go back and fill them in.
[0] http://lkml.kernel.org/g/1465518467-23939-1-git-send-email-mturquette at baylibre.com
Michael Turquette (7):
clk: meson: add peripheral gate macro
clk: meson: add mpll support
clk: meson: fractional pll support
clk: gxbb: Document bindings for the GXBB clock controller
clk: gxbb: add AmLogic GXBB clk controller driver
arm64: amlogic: select gxbb clk driver
arm64: dts: gxbb clock controller.../bindings/clock/amlogic,gxbb-clkc.txt | 36 + arch/arm64/Kconfig.platforms | 2 + arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 7 + drivers/clk/meson/Kconfig | 7 + drivers/clk/meson/Makefile | 3 +- drivers/clk/meson/clk-mpll.c | 94 ++ drivers/clk/meson/clk-pll.c | 32 +- drivers/clk/meson/clkc.h | 39 + drivers/clk/meson/gxbb.c | 954 +++++++++++++++++++++Quoted 9 lines
drivers/clk/meson/gxbb.h | 271 ++++++ include/dt-bindings/clock/gxbb-clkc.h | 12 + 11 files changed, 1454 insertions(+), 3 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/amlogic,gxbb-clkc.txt create mode 100644 drivers/clk/meson/clk-mpll.c create mode 100644 drivers/clk/meson/gxbb.c create mode 100644 drivers/clk/meson/gxbb.h create mode 100644 include/dt-bindings/clock/gxbb-clkc.hMike,
Quoted 8 lines
Quoted 2 lines
I did not receive the 5/7 on the mailing list, can you resend ?
Neil, did you end up receiving this?
The mailing-list had a size limit that caught this one. I bumped it up and approved the mail, so it shold've gone through, and shows in
patchwork: https://patchwork.kernel.org/patch/9170173/
Yes I finally got it.
Isn't the size limit configurable ?
Neil
Quoted 3 lines
Kevin
Kevin Hilman
maintainercover Add support for AmLogic GXBB clock controller
In reply to Michael TurquetteHi Mike,
Quoted 8 lines · Michael Turquette
This series is based on the AmLogic Meson8b rewrite/cleanup[0]. The AmLogic GXBB is an ARMv8-based SoC, fed by a 24MHZ xtal, and it provides several PLLs, muxes dividers and gates to drive CPUs and peripherals.
While based on the Meson8b clock controller driver, this series adds supports for Multi-phase Locked Loops (mpll) and support for PLLs with fractional rates.
Quoted 8 lines
This series introduces the clock controller driver for the gxbb, including the DT binding description and accompanying change in the gxbb dtsi. Only three clocks are exposed via the headers in the dt-bindings include-chroot. More can be added later, but since these values represent an ABI I wanted to start small. I'm not sure about the names for the gate clocks, so I especially tried to avoid putting those in the binding (with the exception of the Ethernet gate, which Kevin has needed for a while).
I tested this on top of my integration branch for v4.7-rc[1] along with the ethernet driver.
First, I modified the ethernet node to use the new clock[2], and then I added the ethernet driver to the build as modules[3] since unloading/reloading the module is testing the clock API[3].
Then, I tested unloading/reloading the dwmac-meson module on meson-gxbb-p200 and meson-gxbb-odroidc2 and found that the system hung on module reload.
As you suggested off-list, this might be because it's walking up the tree and disabling clk81, which would cause such a problem, so I added CLK_IS_CRITICAL to clk81, and that got things working just fine.
With that change, I can now unload/reload the ethernet module (which is prepare/enable'ing and unprepare/disable'ing the clocks.
Kevin
[1] https://git.kernel.org/cgit/linux/kernel/git/khilman/linux-amlogic.git/log/?h=v4.7/integ
[2]
arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi +2 -1
@@ -45,6 +45,7 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/gpio/meson-gxbb-gpio.h> #include <dt-bindings/reset/amlogic,meson-gxbb-reset.h> +#include <dt-bindings/clock/gxbb-clkc.h> / { compatible = "amlogic,meson-gxbb";
@@ -332,7 +333,7 @@ 0x0 0xc8834540 0x0 0x4>; interrupts = <0 8 1>; interrupt-names = "macirq"; - clocks = <&xtal>; + clocks = <&clkc CLKID_ETH>; clock-names = "stmmaceth"; phy-mode = "rgmii"; status = "disabled";
[3]CONFIG_STMMAC_ETH=mCONFIG_PHYLIB=mCONFIG_MICREL_PHY=mCONFIG_REALTEK_PHY=m
[4]
drivers/clk/meson/gxbb.c +1 -1
@@ -558,7 +558,7 @@ static struct clk_gate gxbb_clk81 = { .ops = &clk_gate_ops, .parent_names = (const char *[]){ "mpeg_clk_div" }, .num_parents = 1, - .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED), + .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED | CLK_IS_CRITICAL), }, };
cover Add support for AmLogic GXBB clock controller
Hi Kevin,
Quoting Kevin Hilman (2016-06-14 11:59:10)
Quoted 28 lines
Hi Mike,
Quoted 8 lines · Michael Turquette
This series is based on the AmLogic Meson8b rewrite/cleanup[0]. The AmLogic GXBB is an ARMv8-based SoC, fed by a 24MHZ xtal, and it provides several PLLs, muxes dividers and gates to drive CPUs and peripherals.
While based on the Meson8b clock controller driver, this series adds supports for Multi-phase Locked Loops (mpll) and support for PLLs with fractional rates.
Quoted 8 lines
This series introduces the clock controller driver for the gxbb, including the DT binding description and accompanying change in the gxbb dtsi. Only three clocks are exposed via the headers in the dt-bindings include-chroot. More can be added later, but since these values represent an ABI I wanted to start small. I'm not sure about the names for the gate clocks, so I especially tried to avoid putting those in the binding (with the exception of the Ethernet gate, which Kevin has needed for a while).
I tested this on top of my integration branch for v4.7-rc[1] along with the ethernet driver.
First, I modified the ethernet node to use the new clock[2], and then I added the ethernet driver to the build as modules[3] since unloading/reloading the module is testing the clock API[3].
Quoted 7 lines
Then, I tested unloading/reloading the dwmac-meson module on meson-gxbb-p200 and meson-gxbb-odroidc2 and found that the system hung on module reload.
As you suggested off-list, this might be because it's walking up the tree and disabling clk81, which would cause such a problem, so I added
CLK_IS_CRITICALto clk81, and that got things working just fine.
Great! I'm glad that fixed the problem.
Quoted 5 lines
With that change, I can now unload/reload the ethernet module (which is prepare/enable'ing and unprepare/disable'ing the clocks.
Tested-by Kevin Hilman <[email protected]>
Cool, thanks for testing. I'll fold your change to set the CLK_IS_CRITICAL flag in below on v2, which I'll push to the list early next week after I return from travel.
Regards,
Mike
Quoted 46 lines
Kevin
[1] https://git.kernel.org/cgit/linux/kernel/git/khilman/linux-amlogic.git/log/?h=v4.7/integ
[2]arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi +2
-1@@ -45,6 +45,7 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/gpio/meson-gxbb-gpio.h> #include <dt-bindings/reset/amlogic,meson-gxbb-reset.h> +#include <dt-bindings/clock/gxbb-clkc.h> / { compatible = "amlogic,meson-gxbb";@@ -332,7 +333,7 @@ 0x0 0xc8834540 0x0 0x4>; interrupts = <0 8 1>; interrupt-names = "macirq"; - clocks = <&xtal>; + clocks = <&clkc CLKID_ETH>; clock-names = "stmmaceth"; phy-mode = "rgmii"; status = "disabled";[3]
CONFIG_STMMAC_ETH=mCONFIG_PHYLIB=mCONFIG_MICREL_PHY=mCONFIG_REALTEK_PHY=m[4]
drivers/clk/meson/gxbb.c +1
-1@@ -558,7 +558,7 @@ static struct clk_gate gxbb_clk81 = { .ops = &clk_gate_ops, .parent_names = (const char *[]){ "mpeg_clk_div" }, .num_parents = 1, - .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED), + .flags = (CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED | CLK_IS_CRITICAL), }, };