pinctrl: meson: Add a bunch more pins

PATCH New Kevin Hilman 3 participants 16 messages May 6, 2016 – May 26, 2016

Subsystems (4)

Device tree bindings GPIO Arm/Amlogic Meson SoC support Pin control

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Kevin Hilman

author maintainer

2016-05-06 14:21 UTC #0 lore raw

cover pinctrl: meson: Add a bunch more pins

Add support for several more devices, both in the EE domain and in the AO domain. Also, add the pins to the corresponding DTS files.

Tested on odroid-c2 and Amlogic P200 boards, and verified with working ethernet.

Depends on the initial GXBB pinctrl support from Carlo[1]. Also available in my git tree[2] with all the dependencies included.

Kevin

[1] [PATCH v2 0/4] Amlogic: GXBB: Add pin controller

    http://lists.infradead.org/pipermail/linux-arm-kernel/2016-May/426718.html

[2] https://git.kernel.org/cgit/linux/kernel/git/khilman/linux.git/log/?h=amlogic/wip/pinctrl

Kevin Hilman (7):
pinctrl: amlogic: gxbb: add UART_AO_B, I2C
pinctrl: amlogic: gxbb: add EMMC and SD pins
pinctrl: amlogic: gxbb: add more UART pins pinctrl amlogic: gxbb: add ethernet pins
ARM64: dts: amlogic: add pins for EMMC, SD
ARM64: dts: amlogic: gxbb: pinctrl: add/update UART
ARM64: dts: amlogic: gxbb: add ethernet

 .../arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts |   7 +
 arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi   |   7 +
 arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi        |  97 +++++++++++-
 drivers/pinctrl/meson/pinctrl-meson-gxbb.c         | 167 ++++++++++++++++++++-
 4 files changed, 273 insertions(+), 5 deletions(-)

Signature · 1 line

2.7.4

Kevin Hilman

author maintainer

2016-05-06 14:21 UTC #1 lore raw

PATCH 1/7 pinctrl: amlogic: gxbb: add UART_AO_B, I2C

Add pins for some more AO domain devices: UART_AO_B and I2C master & slave.

Also, rename UART_AO to UART_AO_A since UART_AO_B has also been added.

Cc Carlo Caione <[email protected]>

Signed-off-by Kevin Hilman <[email protected]>

---
 arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi |  2 +-
 drivers/pinctrl/meson/pinctrl-meson-gxbb.c  | 39 ++++++++++++++++++++++++++---
 2 files changed, 37 insertions(+), 4 deletions(-)

arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi +1 -1

index 6dd27685e31e..35397fcc5380 100644
@@ -177,7 +177,7 @@
 				uart_ao_a_pins: uart_ao_a {
 					mux {
 						groups = "uart_tx_ao_a", "uart_rx_ao_a";
-						function = "uart_ao";
+						function = "uart_ao_a";
 					};
 				};
 			};

drivers/pinctrl/meson/pinctrl-meson-gxbb.c +36 -3

index eeabafbbf598..50551677b0ee 100644
@@ -168,6 +168,16 @@ static const unsigned int uart_tx_ao_a_pins[]	= { PIN(GPIOAO_0, 0) };
 static const unsigned int uart_rx_ao_a_pins[]	= { PIN(GPIOAO_1, 0) };
 static const unsigned int uart_cts_ao_a_pins[]	= { PIN(GPIOAO_2, 0) };
 static const unsigned int uart_rts_ao_a_pins[]	= { PIN(GPIOAO_3, 0) };
+static const unsigned int uart_tx_ao_b_pins[]	= { PIN(GPIOAO_0, 0) };
+static const unsigned int uart_rx_ao_b_pins[]	= { PIN(GPIOAO_1, 0),
+						    PIN(GPIOAO_5, 0) };
+static const unsigned int uart_cts_ao_b_pins[]	= { PIN(GPIOAO_2, 0) };
+static const unsigned int uart_rts_ao_b_pins[]	= { PIN(GPIOAO_3, 0) };
+
+static const unsigned int i2c_sck_ao_pins[] = {PIN(GPIOAO_4, 0) };
+static const unsigned int i2c_sda_ao_pins[] = {PIN(GPIOAO_5, 0) };
+static const unsigned int i2c_slave_sck_ao_pins[] = {PIN(GPIOAO_4, 0) };
+static const unsigned int i2c_slave_sda_ao_pins[] = {PIN(GPIOAO_5, 0) };
 
 static struct meson_pmx_group meson_gxbb_periphs_groups[] = {
 	GPIO_GROUP(GPIOZ_0, EE_OFF),

@@ -316,10 +326,18 @@ static struct meson_pmx_group meson_gxbb_aobus_groups[] = {
 	GPIO_GROUP(GPIOAO_13, 0),
 
 	/* bank AO */
+	GROUP(uart_tx_ao_b,	0,	26),
+	GROUP(uart_rx_ao_b,	0,	25),
 	GROUP(uart_tx_ao_a,	0,	12),
 	GROUP(uart_rx_ao_a,	0,	11),
 	GROUP(uart_cts_ao_a,	0,	10),
 	GROUP(uart_rts_ao_a,	0,	9),
+	GROUP(uart_cts_ao_b,	0,	8),
+	GROUP(uart_rts_ao_b,	0,	7),
+	GROUP(i2c_sck_ao,	0,	6),
+	GROUP(i2c_sda_ao,	0,	5),
+	GROUP(i2c_slave_sck_ao, 0,	2),
+	GROUP(i2c_slave_sda_ao, 0,	1),
 };
 
 static const char * const gpio_periphs_groups[] = {

@@ -365,8 +383,20 @@ static const char * const gpio_aobus_groups[] = {
 	"GPIOAO_10", "GPIOAO_11", "GPIOAO_12", "GPIOAO_13",
 };
 
-static const char * const uart_ao_groups[] = {
-	"uart_tx_ao_a", "uart_rx_ao_a", "uart_cts_ao_a", "uart_rts_ao_a"
+static const char * const uart_ao_a_groups[] = {
+	"uart_tx_ao_a", "uart_rx_ao_a", "uart_cts_ao_a", "uart_rts_ao_a",
+};
+
+static const char * const uart_ao_b_groups[] = {
+	"uart_tx_ao_b", "uart_rx_ao_b", "uart_cts_ao_b", "uart_rts_ao_b",
+};
+
+static const char * const i2c_ao_groups[] = {
+	"i2c_sdk_ao", "i2c_sda_ao",
+};
+
+static const char * const i2c_slave_ao_groups[] = {
+	"i2c_slave_sdk_ao", "i2c_slave_sda_ao",
 };
 
 static struct meson_pmx_func meson_gxbb_periphs_functions[] = {

@@ -375,7 +405,10 @@ static struct meson_pmx_func meson_gxbb_periphs_functions[] = {
 
 static struct meson_pmx_func meson_gxbb_aobus_functions[] = {
 	FUNCTION(gpio_aobus),
-	FUNCTION(uart_ao),
+	FUNCTION(uart_ao_a),
+	FUNCTION(uart_ao_b),
+	FUNCTION(i2c_ao),
+	FUNCTION(i2c_slave_ao),
 };
 
 static struct meson_bank meson_gxbb_periphs_banks[] = {

Signature · 1 line

2.7.4

Kevin Hilman

author maintainer

2016-05-06 14:21 UTC #2 lore raw

PATCH 2/7 pinctrl: amlogic: gxbb: add EMMC and SD pins

In reply to Kevin Hilman

Add EE domain pins for eMMC and SD card.

Cc Carlo Caione <[email protected]>

Signed-off-by Kevin Hilman <[email protected]>

---
 drivers/pinctrl/meson/pinctrl-meson-gxbb.c | 41 ++++++++++++++++++++++++++++++
 1 file changed, 41 insertions(+)

drivers/pinctrl/meson/pinctrl-meson-gxbb.c +41 -0

index 50551677b0ee..5dc98ee35265 100644
@@ -147,6 +147,22 @@ static const struct pinctrl_pin_desc meson_gxbb_periphs_pins[] = {
 	MESON_PIN(GPIO_TEST_N, EE_OFF),
 };
 
+static const unsigned int emmc_nand_d07_pins[] = {
+	PIN(BOOT_0, EE_OFF), PIN(BOOT_1, EE_OFF), PIN(BOOT_2, EE_OFF),
+	PIN(BOOT_3, EE_OFF), PIN(BOOT_4, EE_OFF), PIN(BOOT_5, EE_OFF),
+	PIN(BOOT_6, EE_OFF), PIN(BOOT_7, EE_OFF),
+};
+static const unsigned int emmc_clk_pins[] = { PIN(BOOT_8, EE_OFF) };
+static const unsigned int emmc_cmd_pins[] = { PIN(BOOT_10, EE_OFF) };
+static const unsigned int emmc_ds_pins[] = { PIN(BOOT_15, EE_OFF) };
+
+static const unsigned int sdcard_d0_pins[] = { PIN(CARD_1, EE_OFF) };
+static const unsigned int sdcard_d1_pins[] = { PIN(CARD_0, EE_OFF) };
+static const unsigned int sdcard_d2_pins[] = { PIN(CARD_5, EE_OFF) };
+static const unsigned int sdcard_d3_pins[] = { PIN(CARD_4, EE_OFF) };
+static const unsigned int sdcard_cmd_pins[] = { PIN(CARD_3, EE_OFF) };
+static const unsigned int sdcard_clk_pins[] = { PIN(CARD_2, EE_OFF) };
+
 static const struct pinctrl_pin_desc meson_gxbb_aobus_pins[] = {
 	MESON_PIN(GPIOAO_0, 0),
 	MESON_PIN(GPIOAO_1, 0),

@@ -307,6 +323,20 @@ static struct meson_pmx_group meson_gxbb_periphs_groups[] = {
 	GPIO_GROUP(GPIOCLK_3, EE_OFF),
 
 	GPIO_GROUP(GPIO_TEST_N, EE_OFF),
+
+	/* Bank BOOT */
+	GROUP(emmc_nand_d07,	4,	30),
+	GROUP(emmc_clk,		4,	18),
+	GROUP(emmc_cmd,		4,	19),
+	GROUP(emmc_ds,		4,	31),
+
+	/* Bank CARD */
+	GROUP(sdcard_d1,	2,	14),
+	GROUP(sdcard_d0,	2,	15),
+	GROUP(sdcard_d3,	2,	12),
+	GROUP(sdcard_d2,	2,	13),
+	GROUP(sdcard_cmd,	2,	10),
+	GROUP(sdcard_clk,	2,	11),
 };
 
 static struct meson_pmx_group meson_gxbb_aobus_groups[] = {

@@ -377,6 +407,15 @@ static const char * const gpio_periphs_groups[] = {
 	"GPIO_TEST_N",
 };
 
+static const char * const emmc_groups[] = {
+	"emmc_nand_d07", "emmc_clk", "emmc_cmd", "emmc_ds",
+};
+
+static const char * const sdcard_groups[] = {
+	"sdcard_d0", "sdcard_d1", "sdcard_d2", "sdcard_d3",
+	"sdcard_cmd", "sdcard_clk",
+};
+
 static const char * const gpio_aobus_groups[] = {
 	"GPIOAO_0", "GPIOAO_1", "GPIOAO_2", "GPIOAO_3", "GPIOAO_4",
 	"GPIOAO_5", "GPIOAO_6", "GPIOAO_7", "GPIOAO_8", "GPIOAO_9",

@@ -401,6 +440,8 @@ static const char * const i2c_slave_ao_groups[] = {
 
 static struct meson_pmx_func meson_gxbb_periphs_functions[] = {
 	FUNCTION(gpio_periphs),
+	FUNCTION(emmc),
+	FUNCTION(sdcard),
 };
 
 static struct meson_pmx_func meson_gxbb_aobus_functions[] = {

Signature · 1 line

2.7.4

Kevin Hilman

author maintainer

2016-05-06 14:21 UTC #3 lore raw

PATCH 3/7 pinctrl: amlogic: gxbb: add more UART pins

In reply to Kevin Hilman

Add EE domain pins for UART A, B & C.

Cc Carlo Caione <[email protected]>

Signed-off-by Kevin Hilman <[email protected]>

---
 drivers/pinctrl/meson/pinctrl-meson-gxbb.c | 48 ++++++++++++++++++++++++++++++
 1 file changed, 48 insertions(+)

drivers/pinctrl/meson/pinctrl-meson-gxbb.c +48 -0

index 5dc98ee35265..67b5af70e9e9 100644
@@ -163,6 +163,21 @@ static const unsigned int sdcard_d3_pins[] = { PIN(CARD_4, EE_OFF) };
 static const unsigned int sdcard_cmd_pins[] = { PIN(CARD_3, EE_OFF) };
 static const unsigned int sdcard_clk_pins[] = { PIN(CARD_2, EE_OFF) };
 
+static const unsigned int uart_tx_a_pins[]	= { PIN(GPIOX_12, EE_OFF) };
+static const unsigned int uart_rx_a_pins[]	= { PIN(GPIOX_13, EE_OFF) };
+static const unsigned int uart_cts_a_pins[]	= { PIN(GPIOX_14, EE_OFF) };
+static const unsigned int uart_rts_a_pins[]	= { PIN(GPIOX_15, EE_OFF) };
+
+static const unsigned int uart_tx_b_pins[]	= { PIN(GPIODV_24, EE_OFF) };
+static const unsigned int uart_rx_b_pins[]	= { PIN(GPIODV_25, EE_OFF) };
+static const unsigned int uart_cts_b_pins[]	= { PIN(GPIODV_26, EE_OFF) };
+static const unsigned int uart_rts_b_pins[]	= { PIN(GPIODV_27, EE_OFF) };
+
+static const unsigned int uart_tx_c_pins[]	= { PIN(GPIOY_13, EE_OFF) };
+static const unsigned int uart_rx_c_pins[]	= { PIN(GPIOY_14, EE_OFF) };
+static const unsigned int uart_cts_c_pins[]	= { PIN(GPIOX_11, EE_OFF) };
+static const unsigned int uart_rts_c_pins[]	= { PIN(GPIOX_12, EE_OFF) };
+
 static const struct pinctrl_pin_desc meson_gxbb_aobus_pins[] = {
 	MESON_PIN(GPIOAO_0, 0),
 	MESON_PIN(GPIOAO_1, 0),

@@ -324,6 +339,24 @@ static struct meson_pmx_group meson_gxbb_periphs_groups[] = {
 
 	GPIO_GROUP(GPIO_TEST_N, EE_OFF),
 
+	/* Bank X */
+	GROUP(uart_tx_a,	4,	13),
+	GROUP(uart_rx_a,	4,	12),
+	GROUP(uart_cts_a,	4,	11),
+	GROUP(uart_rts_a,	4,	10),
+
+	/* Bank Y */
+	GROUP(uart_cts_c,	1,	19),
+	GROUP(uart_rts_c,	1,	18),
+	GROUP(uart_tx_c,	1,	17),
+	GROUP(uart_rx_c,	1,	16),
+
+	/* Bank DV */
+	GROUP(uart_tx_b,	2,	29),
+	GROUP(uart_rx_b,	2,	28),
+	GROUP(uart_cts_b,	2,	27),
+	GROUP(uart_rts_b,	2,	26),
+
 	/* Bank BOOT */
 	GROUP(emmc_nand_d07,	4,	30),
 	GROUP(emmc_clk,		4,	18),

@@ -416,6 +449,18 @@ static const char * const sdcard_groups[] = {
 	"sdcard_cmd", "sdcard_clk",
 };
 
+static const char * const uart_a_groups[] = {
+	"uart_tx_a", "uart_rx_a", "uart_cts_a", "uart_rts_a",
+};
+
+static const char * const uart_b_groups[] = {
+	"uart_tx_b", "uart_rx_b", "uart_cts_b", "uart_rts_b",
+};
+
+static const char * const uart_c_groups[] = {
+	"uart_tx_c", "uart_rx_c", "uart_cts_c", "uart_rts_c",
+};
+
 static const char * const gpio_aobus_groups[] = {
 	"GPIOAO_0", "GPIOAO_1", "GPIOAO_2", "GPIOAO_3", "GPIOAO_4",
 	"GPIOAO_5", "GPIOAO_6", "GPIOAO_7", "GPIOAO_8", "GPIOAO_9",

@@ -442,6 +487,9 @@ static struct meson_pmx_func meson_gxbb_periphs_functions[] = {
 	FUNCTION(gpio_periphs),
 	FUNCTION(emmc),
 	FUNCTION(sdcard),
+	FUNCTION(uart_a),
+	FUNCTION(uart_b),
+	FUNCTION(uart_c),
 };
 
 static struct meson_pmx_func meson_gxbb_aobus_functions[] = {

Signature · 1 line

2.7.4

Kevin Hilman

author maintainer

2016-05-06 14:21 UTC #4 lore raw

PATCH 4/7 pinctrl amlogic: gxbb: add ethernet pins

In reply to Kevin Hilman

Add EE domain pins for ethernet interface.

Signed-off-by Kevin Hilman <[email protected]>

---
 drivers/pinctrl/meson/pinctrl-meson-gxbb.c | 39 ++++++++++++++++++++++++++++++
 1 file changed, 39 insertions(+)

drivers/pinctrl/meson/pinctrl-meson-gxbb.c +39 -0

index 67b5af70e9e9..360535a30625 100644
@@ -178,6 +178,21 @@ static const unsigned int uart_rx_c_pins[]	= { PIN(GPIOY_14, EE_OFF) };
 static const unsigned int uart_cts_c_pins[]	= { PIN(GPIOX_11, EE_OFF) };
 static const unsigned int uart_rts_c_pins[]	= { PIN(GPIOX_12, EE_OFF) };
 
+static const unsigned int eth_mdio_pins[]	= { PIN(GPIOZ_0, EE_OFF) };
+static const unsigned int eth_mdc_pins[]	= { PIN(GPIOZ_1, EE_OFF) };
+static const unsigned int eth_clk_rx_clk_pins[]	= { PIN(GPIOZ_2, EE_OFF) };
+static const unsigned int eth_rx_dv_pins[]	= { PIN(GPIOZ_3, EE_OFF) };
+static const unsigned int eth_rxd0_pins[]	= { PIN(GPIOZ_4, EE_OFF) };
+static const unsigned int eth_rxd1_pins[]	= { PIN(GPIOZ_5, EE_OFF) };
+static const unsigned int eth_rxd2_pins[]	= { PIN(GPIOZ_6, EE_OFF) };
+static const unsigned int eth_rxd3_pins[]	= { PIN(GPIOZ_7, EE_OFF) };
+static const unsigned int eth_rgmii_tx_clk_pins[] = { PIN(GPIOZ_8, EE_OFF) };
+static const unsigned int eth_tx_en_pins[]	= { PIN(GPIOZ_9, EE_OFF) };
+static const unsigned int eth_txd0_pins[]	= { PIN(GPIOZ_10, EE_OFF) };
+static const unsigned int eth_txd1_pins[]	= { PIN(GPIOZ_11, EE_OFF) };
+static const unsigned int eth_txd2_pins[]	= { PIN(GPIOZ_12, EE_OFF) };
+static const unsigned int eth_txd3_pins[]	= { PIN(GPIOZ_13, EE_OFF) };
+
 static const struct pinctrl_pin_desc meson_gxbb_aobus_pins[] = {
 	MESON_PIN(GPIOAO_0, 0),
 	MESON_PIN(GPIOAO_1, 0),

@@ -351,6 +366,22 @@ static struct meson_pmx_group meson_gxbb_periphs_groups[] = {
 	GROUP(uart_tx_c,	1,	17),
 	GROUP(uart_rx_c,	1,	16),
 
+	/* Bank Z */
+	GROUP(eth_mdio,		6,	1),
+	GROUP(eth_mdc,		6,	0),
+	GROUP(eth_clk_rx_clk,	6,	13),
+	GROUP(eth_rx_dv,	6,	12),
+	GROUP(eth_rxd0,		6,	11),
+	GROUP(eth_rxd1,		6,	10),
+	GROUP(eth_rxd2,		6,	9),
+	GROUP(eth_rxd3,		6,	8),
+	GROUP(eth_rgmii_tx_clk,	6,	7),
+	GROUP(eth_tx_en,	6,	6),
+	GROUP(eth_txd0,		6,	5),
+	GROUP(eth_txd1,		6,	4),
+	GROUP(eth_txd2,		6,	3),
+	GROUP(eth_txd3,		6,	2),
+
 	/* Bank DV */
 	GROUP(uart_tx_b,	2,	29),
 	GROUP(uart_rx_b,	2,	28),

@@ -461,6 +492,13 @@ static const char * const uart_c_groups[] = {
 	"uart_tx_c", "uart_rx_c", "uart_cts_c", "uart_rts_c",
 };
 
+static const char * const eth_groups[] = {
+	"eth_mdio", "eth_mdc", "eth_clk_rx_clk", "eth_rx_dv",
+	"eth_rxd0", "eth_rxd1", "eth_rxd2", "eth_rxd3",
+	"eth_rgmii_tx_clk", "eth_tx_en",
+	"eth_txd0", "eth_txd1", "eth_txd2", "eth_txd3",
+};
+
 static const char * const gpio_aobus_groups[] = {
 	"GPIOAO_0", "GPIOAO_1", "GPIOAO_2", "GPIOAO_3", "GPIOAO_4",
 	"GPIOAO_5", "GPIOAO_6", "GPIOAO_7", "GPIOAO_8", "GPIOAO_9",

@@ -490,6 +528,7 @@ static struct meson_pmx_func meson_gxbb_periphs_functions[] = {
 	FUNCTION(uart_a),
 	FUNCTION(uart_b),
 	FUNCTION(uart_c),
+	FUNCTION(eth),
 };
 
 static struct meson_pmx_func meson_gxbb_aobus_functions[] = {

Signature · 1 line

2.7.4

Kevin Hilman

author maintainer

2016-05-06 14:21 UTC #5 lore raw

PATCH 5/7 ARM64: dts: amlogic: add pins for EMMC, SD

In reply to Kevin Hilman

Signed-off-by Kevin Hilman <[email protected]>

---
 arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi +21 -0

index 35397fcc5380..7b22b9d3b9d9 100644
@@ -213,6 +213,27 @@
 					gpio-controller;
 					#gpio-cells = <2>;
 				};
+
+				emmc_pins: emmc {
+					mux {
+						groups = "emmc_nand_d07",
+						       "emmc_cmd",
+						       "emmc_clk";
+						function = "emmc";
+					};
+				};
+
+				sdcard_pins: sdcard {
+					mux {
+						groups = "sdcard_d0",
+						       "sdcard_d1",
+						       "sdcard_d2",
+						       "sdcard_d3",
+						       "sdcard_cmd",
+						       "sdcard_clk";
+						function = "sdcard";
+					};
+				};
 			};
 		};

Signature · 1 line

2.7.4

Kevin Hilman

author maintainer

2016-05-06 14:21 UTC #6 lore raw

PATCH 6/7 ARM64: dts: amlogic: gxbb: pinctrl: add/update UART

In reply to Kevin Hilman

Add DT nodes for additional UARTs (UART B & C in EE domain) and add pins for all EE domain UARTs.

Signed-off-by Kevin Hilman <[email protected]>

---
 .../arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts |  1 +
 arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi        | 42 +++++++++++++++++++++-
 2 files changed, 42 insertions(+), 1 deletion(-)

arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts +1 -0

index 41e1e669bc70..45778896bd3d 100644
@@ -80,3 +80,4 @@
 	pinctrl-0 = <&uart_ao_a_pins>;
 	pinctrl-names = "default";
 };
+

arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi +41 -1

58 lines not on this page · raw message

Signature · 1 line

2.7.4

Kevin Hilman

author maintainer

2016-05-06 14:21 UTC #7 lore raw

PATCH 7/7 ARM64: dts: amlogic: gxbb: add ethernet

In reply to Kevin Hilman

Add node for ethernet interface and pinctrl pins.
Enable on odroid-C2 and P20x boards.

Signed-off-by Kevin Hilman <[email protected]>

---
 .../arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts |  6 ++++
 arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi   |  7 +++++
 arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi        | 32 ++++++++++++++++++++++
 3 files changed, 45 insertions(+)

arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts +6 -0

index 45778896bd3d..90a84c514d3d 100644
@@ -81,3 +81,9 @@
 	pinctrl-names = "default";
 };
 
+&ethmac {
+	status = "okay";
+	pinctrl-0 = <&eth_pins>;
+	pinctrl-names = "default";
+};
+

arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi +7 -0

index 22e629841a99..f4f30f674b4c 100644
@@ -65,3 +65,10 @@
 	pinctrl-0 = <&uart_ao_a_pins>;
 	pinctrl-names = "default";
 };
+
+&ethmac {
+	status = "okay";
+	pinctrl-0 = <&eth_pins>;
+	pinctrl-names = "default";
+};
+

arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi +32 -0

index 86c41b3798db..76b3b6d0526b 100644
@@ -274,6 +274,26 @@
 						function = "uart_c";
 					};
 				};
+
+				eth_pins: eth_c {
+					mux {
+						groups = "eth_mdio",
+						       "eth_mdc",
+						       "eth_clk_rx_clk",
+						       "eth_rx_dv",
+						       "eth_rxd0",
+						       "eth_rxd1",
+						       "eth_rxd2",
+						       "eth_rxd3",
+						       "eth_rgmii_tx_clk",
+						       "eth_tx_en",
+						       "eth_txd0",
+						       "eth_txd1",
+						       "eth_txd2",
+						       "eth_txd3";
+						function = "eth";
+					};
+				};
 			};
 		};

@@ -292,5 +312,17 @@
 			#size-cells = <2>;
 			ranges = <0x0 0x0 0x0 0xd0000000 0x0 0x200000>;
 		};
+
+		ethmac: ethernet at c9410000 {
+			compatible = "amlogic,meson6-dwmac", "snps,dwmac";
+			reg = <0x0 0xc9410000 0x0 0x10000
+			       0x0 0xc8834540 0x0 0x4>;
+			interrupts = <0 8 1>;
+			interrupt-names = "macirq";
+			clocks = <&xtal>;
+			clock-names = "stmmaceth";
+			phy-mode = "rgmii";
+			status = "disabled";
+		};
 	};
 };

Signature · 1 line

2.7.4

Linus Walleij

2016-05-11 08:57 UTC #8 lore raw

cover pinctrl: meson: Add a bunch more pins

In reply to Kevin Hilman

Quoted 8 lines · Kevin Hilman

Add support for several more devices, both in the EE domain and in the AO domain. Also, add the pins to the corresponding DTS files.
Tested on odroid-c2 and Amlogic P200 boards, and verified with working ethernet.
Depends on the initial GXBB pinctrl support from Carlo[1]. Also available in my git tree[2] with all the dependencies included.

Carlo can you review Kevin's patches? I'd like to apply them if nothing's controversial about them.

Yours,
Linus Walleij

Carlo Caione

2016-05-11 09:18 UTC #9 lore raw

cover pinctrl: meson: Add a bunch more pins

Quoted 5 lines · Linus Walleij

Quoted 3 lines · Kevin Hilman
Add support for several more devices, both in the EE domain and in the AO domain. Also, add the pins to the corresponding DTS files.

Quoted 8 lines

Quoted 5 lines
Tested on odroid-c2 and Amlogic P200 boards, and verified with working ethernet.
Depends on the initial GXBB pinctrl support from Carlo[1]. Also available in my git tree[2] with all the dependencies included.
Carlo can you review Kevin's patches? I'd like to apply them if nothing's controversial about them.

Go ahead and apply them:

Acked-by Carlo Caione <[email protected]>

The ack is on the formal correctness since I still do not have access to the datasheet.

Thanks,

Signature · 1 line

Carlo Caione

Linus Walleij

2016-05-24 09:23 UTC #10 lore raw

cover pinctrl: meson: Add a bunch more pins

In reply to Kevin Hilman

Quoted 8 lines · Kevin Hilman

Add support for several more devices, both in the EE domain and in the AO domain. Also, add the pins to the corresponding DTS files.
Tested on odroid-c2 and Amlogic P200 boards, and verified with working ethernet.
Depends on the initial GXBB pinctrl support from Carlo[1]. Also available in my git tree[2] with all the dependencies included.

These don't apply anomore sadly, Kevin can you rebase on Torvalds' HEAD and resend, and include Carlo's ACK on them so I can merge them in the next kernel cycle?

Yours,
Linus Walleij

Kevin Hilman

author maintainer

2016-05-24 16:14 UTC #11 lore raw

cover pinctrl: meson: Add a bunch more pins

Quoted 8 lines · Linus Walleij

Quoted 6 lines · Kevin Hilman
Add support for several more devices, both in the EE domain and in the AO domain. Also, add the pins to the corresponding DTS files.
Tested on odroid-c2 and Amlogic P200 boards, and verified with working ethernet.

Quoted 6 lines

Quoted 2 lines
Depends on the initial GXBB pinctrl support from Carlo[1]. Also available in my git tree[2] with all the dependencies included.
These don't apply anomore sadly, Kevin can you rebase on Torvalds' HEAD and resend, and include Carlo's ACK on them so I can merge them in the next kernel cycle?

Coming right up...

Kevin

Kevin Hilman

author maintainer

2016-05-24 18:29 UTC #12 lore raw

cover pinctrl: meson: Add a bunch more pins

In reply to Linus Walleij

Quoted 8 lines · Linus Walleij

Quoted 6 lines · Kevin Hilman
Add support for several more devices, both in the EE domain and in the AO domain. Also, add the pins to the corresponding DTS files.
Tested on odroid-c2 and Amlogic P200 boards, and verified with working ethernet.

Quoted 6 lines

Quoted 2 lines
Depends on the initial GXBB pinctrl support from Carlo[1]. Also available in my git tree[2] with all the dependencies included.
These don't apply anomore sadly, Kevin can you rebase on Torvalds' HEAD and resend, and include Carlo's ACK on them so I can merge them in the next kernel cycle?

Looking closer, these have dependencies on the DT changes that you've suggested we take through arm-soc, so it would be cleaner if I take these with your ack through the amlogic tree.

Since it's a brand new driver, I don't expect there to be conflicts.

Does that work for you?

Kevin

Kevin Hilman

author maintainer

2016-05-24 21:45 UTC #13 lore raw

cover pinctrl: meson: Add a bunch more pins

Quoted 17 lines · Kevin Hilman

Quoted 8 lines · Linus Walleij
Quoted 6 lines · Kevin Hilman
Add support for several more devices, both in the EE domain and in the AO domain. Also, add the pins to the corresponding DTS files.
Tested on odroid-c2 and Amlogic P200 boards, and verified with working ethernet.
Quoted 6 lines
Quoted 2 lines
Depends on the initial GXBB pinctrl support from Carlo[1]. Also available in my git tree[2] with all the dependencies included.
These don't apply anomore sadly, Kevin can you rebase on Torvalds' HEAD and resend, and include Carlo's ACK on them so I can merge them in the next kernel cycle?

Quoted 7 lines

Looking closer, these have dependencies on the DT changes that you've suggested we take through arm-soc, so it would be cleaner if I take these with your ack through the amlogic tree.
Since it's a brand new driver, I don't expect there to be conflicts.
Does that work for you?

FWIW, rebase available here (with all deps, some of which I think you'ved already merged):

git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux.git amlogic/v4.7/pinctrl

Kevin

Linus Walleij

2016-05-26 09:28 UTC #14 lore raw

cover pinctrl: meson: Add a bunch more pins

In reply to Kevin Hilman

Quoted 5 lines · Kevin Hilman

Linus Walleij <[email protected]> writes:
Looking closer, these have dependencies on the DT changes that you've suggested we take through arm-soc, so it would be cleaner if I take these with your ack through the amlogic tree.

I really prefer to take DT changes and driver code in different trees i possible.

My reasoning is plainly: if the DT stuff was a separate git, as has been explicitly suggested as a goal off and on, this should be merge:able still. So DT changes and driver code should ideally be orthogonal.

I don't know about this case but is it a disaster if one or the other of the DT changes and the driver arrive in different order to Torvald's tree, or will it simply be that the lights go on when the last patch arrives?

Yours,
Linus Walleij

Kevin Hilman

author maintainer

2016-05-26 21:05 UTC #15 lore raw

cover pinctrl: meson: Add a bunch more pins

Quoted 15 lines · Linus Walleij

Quoted 5 lines · Kevin Hilman
Linus Walleij <[email protected]> writes:
Looking closer, these have dependencies on the DT changes that you've suggested we take through arm-soc, so it would be cleaner if I take these with your ack through the amlogic tree.
I really prefer to take DT changes and driver code in different trees i possible.
My reasoning is plainly: if the DT stuff was a separate git, as has been explicitly suggested as a goal off and on, this should be merge:able still. So DT changes and driver code should ideally be orthogonal.

Quoted 4 lines

I don't know about this case but is it a disaster if one or the other of the DT changes and the driver arrive in different order to Torvald's tree, or will it simply be that the lights go on when the last patch arrives?

Actually, it wasn't about built/boot dependencies but rather one of the patches (mistakenly) had both a pinctrl change and a DT change, so a simple rebase failed (and I gave up early since I was busy with something else... and also lazy.)

Anyways, I've now separated things, so the pinctrl patches can go through your tree, and we'll submit the rest (DT, kconfig etc.) through arm-soc, and things will "just work" when they both land in mainline.

I'll repost the series shortly, but if you prefer to just pull, the pinctrl-only stuff based on linus/master is here:

git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux.git amlogic/v4.7/pinctrl-drv

Thanks for the nudge in the right direction,

Kevin