TQMA31: new board

index a218329..6f9306f 100644
@@ -115,6 +115,16 @@ static int rx_byte(void)
 int i2c_probe(uchar chip)
 {
 	int ret;
+	int timeout = 100000;
+
+	/* Check if bus is busy before probing next chip */
+	while ((__REG16(I2C_BASE + I2SR) & I2SR_IBB) && --timeout)
+		udelay(1);
+
+	if (timeout == 0) {
+		printf ("\nerror: bus blocked\n");
+		return -1;
+	}
 
 	__REG16(I2C_BASE + I2CR) = 0; /* Reset module */
 	__REG16(I2C_BASE + I2CR) = I2CR_IEN;

index 29c08c1..bf4c99c 100644
@@ -27,8 +27,8 @@
 static u32 mx31_decode_pll(u32 reg, u32 infreq)
 {
 	u32 mfi = (reg >> 10) & 0xf;
-	u32 mfn = reg & 0x3f;
-	u32 mfd = (reg >> 16) & 0x3f;
+	u32 mfn = reg & 0x3ff;
+	u32 mfd = (reg >> 16) & 0x3ff;
 	u32 pd =  (reg >> 26) & 0xf;
 
 	mfi = mfi <= 5 ? 5 : mfi;

index 263dd9f..8cbc26e 100644
@@ -50,7 +50,7 @@ int board_init (void)
 	mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
 	mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX);
 	mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
-	mx31_gpio_mux(MUX_RTS1__UART1_CTS_B);
+	mx31_gpio_mux(MUX_CTS1__UART1_CTS_B);
 
 	/* SPI2 */
 	mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_SS2);

index 42ecb1e..ae93444 100644
@@ -54,11 +54,11 @@ int board_init (void)
 	mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
 	mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX);
 	mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
-	mx31_gpio_mux(MUX_RTS1__UART1_CTS_B);
+	mx31_gpio_mux(MUX_CTS1__UART1_CTS_B);
 
 	/* setup pins for I2C2 (for EEPROM, RTC) */
 	mx31_gpio_mux(MUX_CSPI2_MOSI__I2C2_SCL);
-	mx31_gpio_mux(MUX_CSPI2_MISO__I2C2_SCL);
+	mx31_gpio_mux(MUX_CSPI2_MISO__I2C2_SDA);
 
 	gd->bd->bi_arch_number = 447;		/* board id for linux */
 	gd->bd->bi_boot_params = (0x80000100);	/* adress of boot parameters */

index dd0e150..b6928fc 100644
@@ -55,7 +55,7 @@ int board_init (void)
 	mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
 	mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX);
 	mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
-	mx31_gpio_mux(MUX_RTS1__UART1_CTS_B);
+	mx31_gpio_mux(MUX_CTS1__UART1_CTS_B);
 
 	/* SPI2 */
 	mx31_gpio_mux((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_SS2);

index 02b7dcb..abe61f0 100644
@@ -133,10 +133,10 @@
 #define MUX_RXD1__UART1_RXD_MUX	((MUX_CTL_FUNC << 8) | MUX_CTL_RXD1)
 #define MUX_TXD1__UART1_TXD_MUX	((MUX_CTL_FUNC << 8) | MUX_CTL_TXD1)
 #define MUX_RTS1__UART1_RTS_B	((MUX_CTL_FUNC << 8) | MUX_CTL_RTS1)
-#define MUX_RTS1__UART1_CTS_B	((MUX_CTL_FUNC << 8) | MUX_CTL_CTS1)
+#define MUX_CTS1__UART1_CTS_B	((MUX_CTL_FUNC << 8) | MUX_CTL_CTS1)
 
 #define MUX_CSPI2_MOSI__I2C2_SCL ((MUX_CTL_ALT1 << 8) | MUX_CTL_CSPI2_MOSI)
-#define MUX_CSPI2_MISO__I2C2_SCL ((MUX_CTL_ALT1 << 8) | MUX_CTL_CSPI2_MISO)
+#define MUX_CSPI2_MISO__I2C2_SDA ((MUX_CTL_ALT1 << 8) | MUX_CTL_CSPI2_MISO)
 
 /*
  * Memory regions and CS

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index 7cec8db..0c67af3 100644
@@ -49,6 +49,12 @@ static void setup_iomux (void)
 	mx31_gpio_mux (MUX_TXD1__UART1_TXD_MUX);
 	mx31_gpio_mux (MUX_RTS1__UART1_RTS_B);
 	mx31_gpio_mux (MUX_CTS1__UART1_CTS_B);
+
+	/* Pins for I2C1 */
+	mx31_gpio_mux (MUX_I2C_CLK__I2C1_SCL);
+	mx31_gpio_mux (MUX_I2C_DAT__I2C1_SDA);
+	mx31_pad_ctl (PAD_CTL_I2C_CLK, PAD_CTL_IPP_ODE_OD);
+	mx31_pad_ctl (PAD_CTL_I2C_DAT, PAD_CTL_IPP_ODE_OD);
 }
 
 int dram_init (void)

index bf4c99c..9999e12 100644
@@ -90,6 +90,23 @@ void mx31_gpio_mux(unsigned long mode)
 	__REG(reg) = tmp;
 }
 
+void mx31_pad_ctl (u32 field, u32 val)
+{
+	u32 reg, shift, mask, tmp;
+
+	/* extract 32 bit register address and shifter for bit field */
+	reg = IOMUXC_BASE + (field >> 8);
+	shift = field & 0xFF;
+
+	/* field consists of 10 bits */
+	mask = 0x3FF << shift;
+
+	tmp = __REG(reg);
+	tmp &= ~mask;
+	tmp |= (val << shift) & mask;
+	__REG(reg) = tmp;
+}
+
 #if defined(CONFIG_DISPLAY_CPUINFO)
 int print_cpuinfo (void)
 {

index 6f9306f..68d2720 100644
@@ -209,4 +209,17 @@ int i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len)
 	return 0;
 }
 
+int i2c_get_bus_speed(void)
+{
+	return -1;
+}
+
+int i2c_set_bus_speed (unsigned int speed)
+{
+	if (speed != CFG_I2C_SPEED)
+		return -1;
+
+	return 0;
+}
+
 #endif /* CONFIG_HARD_I2C */

index ea15108..c0e516f 100644
@@ -168,6 +168,9 @@
 #define MUX_CTL_CSPI2_SS2	0x87
 #define MUX_CTL_CSPI2_MOSI	0x8b
 
+#define MUX_CTL_I2C_CLK		0xa2
+#define MUX_CTL_I2C_DAT		0xa3
+
 /* The modes a specific pin can be in
  * these macros can be used in mx31_gpio_mux() and have the form
  * MUX_[contact name]__[pin function]

@@ -180,6 +183,35 @@
 #define MUX_CSPI2_MOSI__I2C2_SCL ((MUX_CTL_ALT1 << 8) | MUX_CTL_CSPI2_MOSI)
 #define MUX_CSPI2_MISO__I2C2_SDA ((MUX_CTL_ALT1 << 8) | MUX_CTL_CSPI2_MISO)
 
+#define MUX_I2C_CLK__I2C1_SCL	((MUX_CTL_FUNC << 8) | MUX_CTL_I2C_CLK)
+#define MUX_I2C_DAT__I2C1_SDA	((MUX_CTL_FUNC << 8) | MUX_CTL_I2C_DAT)
+
+/* bits in the SW_PAD_CTL registers */
+#define PAD_CTL_LOOPBACK_DIS		(0 << 9)
+#define PAD_CTL_LOOPBACK_ENA		(1 << 9)
+#define PAD_CTL_IPP_PUE_DIS		(0 << 7)
+#define PAD_CTL_IPP_PUE_KEEPER		(2 << 7)
+#define PAD_CTL_IPP_PUE_PULL		(3 << 7)
+#define PAD_CTL_IPP_PUS_100K_DN		(0 << 5)
+#define PAD_CTL_IPP_PUS_100K_UP		(1 << 5)
+#define PAD_CTL_IPP_HYS_STD		(0 << 4)
+#define PAD_CTL_IPP_HYS_SCHMITT		(1 << 4)
+#define PAD_CTL_IPP_ODE_STD		(0 << 3)
+#define PAD_CTL_IPP_ODE_OD		(1 << 3)
+#define PAD_CTL_IPP_DSE_STD		(0 << 1)
+#define PAD_CTL_IPP_DSE_HIGH		(1 << 1)
+#define PAD_CTL_IPP_DSE_MAX		(2 << 1)
+#define PAD_CTL_IPP_SRE_SLOW		(0 << 0)
+#define PAD_CTL_IPP_SRE_FAST		(1 << 0)
+
+/* bit fields in the SW_PAD_CTL registers, offsets based on IOMUXC_BASE */
+#define	PAD_CTL_IO1_SHIFT		0
+#define	PAD_CTL_IO2_SHIFT		10
+#define	PAD_CTL_IO3_SHIFT		20
+#define PAD_CTL_I2C_CLK			((0x21C << 8) | PAD_CTL_IO2_SHIFT)
+#define PAD_CTL_I2C_DAT			((0x21C << 8) | PAD_CTL_IO1_SHIFT)
+
+
 /*
  * Memory regions and CS
  */

index 0552c27..7b784e6 100644
@@ -26,5 +26,6 @@
 
 extern u32 mx31_get_ipg_clk(void);
 extern void mx31_gpio_mux(unsigned long mode);
+extern void mx31_pad_ctl (u32 field, u32 val);
 
 #endif /* __ASM_ARCH_MX31_H */

index 255355d..f96fd74 100644
@@ -154,6 +154,43 @@
 
 
 /*******************************************************************************
+ * I2C
+ ******************************************************************************/
+
+/* Use the processor internal controller */
+#define CONFIG_HARD_I2C
+#define CONFIG_I2C_MXC
+
+/* Configure I2C1 */
+#define CFG_I2C_MX31_PORT1
+
+#define CFG_I2C_SPEED 			100000
+#define CFG_I2C_SLAVE 			0
+
+/* Don't probe these addrs */
+#define CFG_I2C_NOPROBES		{0x00}
+
+/* I2C EEPROM, configuration for onboard EEPROM */
+#define CFG_I2C_EEPROM_ADDR		0x50
+#define CFG_I2C_EEPROM_ADDR_LEN		2
+
+/* 32 bytes per write */
+#define CFG_EEPROM_PAGE_WRITE_BITS	5
+
+#define CFG_EEPROM_PAGE_WRITE_ENABLE
+
+/* 10ms +/- 20% */
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	12
+
+/* I2C SYSMON (LM75) */
+#define CONFIG_DTT_LM75			1	/* ON Semi's LM75 */
+#define CONFIG_DTT_SENSORS		{0}	/* Sensor addresses */
+#define CFG_DTT_MAX_TEMP		70
+#define CFG_DTT_LOW_TEMP		-30
+#define CFG_DTT_HYSTERESIS		3
+
+
+/*******************************************************************************
  * Commands
  ******************************************************************************/
 

@@ -161,6 +198,9 @@
 
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_DHCP
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_DTT
+#define CONFIG_CMD_EEPROM
 
 
 /*******************************************************************************

index 0c67af3..c704c41 100644
@@ -55,6 +55,19 @@ static void setup_iomux (void)
 	mx31_gpio_mux (MUX_I2C_DAT__I2C1_SDA);
 	mx31_pad_ctl (PAD_CTL_I2C_CLK, PAD_CTL_IPP_ODE_OD);
 	mx31_pad_ctl (PAD_CTL_I2C_DAT, PAD_CTL_IPP_ODE_OD);
+
+	/* Pins for SPI2 */
+	mx31_gpio_mux (MUX_CSPI2_MOSI__CSPI2_MOSI);
+	mx31_gpio_mux (MUX_CSPI2_MISO__CSPI2_MISO);
+	mx31_gpio_mux (MUX_CSPI2_SS0__CSPI2_SS0_B);
+	mx31_gpio_mux (MUX_CSPI2_SCLK__CSPI2_CLK);
+	mx31_pad_ctl (PAD_CTL_CSPI2_SS0, 0);
+	mx31_pad_ctl (PAD_CTL_CSPI2_SS1, 0);
+	mx31_pad_ctl (PAD_CTL_CSPI2_SS2, 0);
+	mx31_pad_ctl (PAD_CTL_CSPI2_SCLK, 0);
+	mx31_pad_ctl (PAD_CTL_CSPI2_SPI_RDY, 0);
+	mx31_pad_ctl (PAD_CTL_CSPI2_MISO, 0);
+	mx31_pad_ctl (PAD_CTL_CSPI2_MOSI, 0);
 }
 
 int dram_init (void)

index c0e516f..4d661e8 100644
@@ -183,6 +183,11 @@
 #define MUX_CSPI2_MOSI__I2C2_SCL ((MUX_CTL_ALT1 << 8) | MUX_CTL_CSPI2_MOSI)
 #define MUX_CSPI2_MISO__I2C2_SDA ((MUX_CTL_ALT1 << 8) | MUX_CTL_CSPI2_MISO)
 
+#define MUX_CSPI2_MOSI__CSPI2_MOSI ((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_MOSI)
+#define MUX_CSPI2_MISO__CSPI2_MISO ((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_MISO)
+#define MUX_CSPI2_SS0__CSPI2_SS0_B ((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_SS0)
+#define MUX_CSPI2_SCLK__CSPI2_CLK  ((MUX_CTL_FUNC << 8) | MUX_CTL_CSPI2_SCLK)
+
 #define MUX_I2C_CLK__I2C1_SCL	((MUX_CTL_FUNC << 8) | MUX_CTL_I2C_CLK)
 #define MUX_I2C_DAT__I2C1_SDA	((MUX_CTL_FUNC << 8) | MUX_CTL_I2C_DAT)
 

@@ -208,6 +213,13 @@
 #define	PAD_CTL_IO1_SHIFT		0
 #define	PAD_CTL_IO2_SHIFT		10
 #define	PAD_CTL_IO3_SHIFT		20
+#define PAD_CTL_CSPI2_SS2		((0x1F4 << 8) | PAD_CTL_IO3_SHIFT)
+#define PAD_CTL_CSPI2_SCLK		((0x1F4 << 8) | PAD_CTL_IO2_SHIFT)
+#define PAD_CTL_CSPI2_SPI_RDY		((0x1F4 << 8) | PAD_CTL_IO1_SHIFT)
+#define PAD_CTL_CSPI2_MISO		((0x1F8 << 8) | PAD_CTL_IO3_SHIFT)
+#define PAD_CTL_CSPI2_SS0		((0x1F8 << 8) | PAD_CTL_IO2_SHIFT)
+#define PAD_CTL_CSPI2_SS1		((0x1F8 << 8) | PAD_CTL_IO1_SHIFT)
+#define PAD_CTL_CSPI2_MOSI		((0x1FC << 8) | PAD_CTL_IO1_SHIFT)
 #define PAD_CTL_I2C_CLK			((0x21C << 8) | PAD_CTL_IO2_SHIFT)
 #define PAD_CTL_I2C_DAT			((0x21C << 8) | PAD_CTL_IO1_SHIFT)
 

index f96fd74..ac81a32 100644
@@ -191,6 +191,24 @@
 
 
 /*******************************************************************************
+ * SPI
+ ******************************************************************************/
+
+/* Use the processor internal controller */
+#define CONFIG_HARD_SPI			1
+#define CONFIG_MXC_SPI			1
+
+/* 0=CSPI1, 1=CSPI2, 2=CSPI3 */
+#define CONFIG_DEFAULT_SPI_BUS		1
+
+/* SCLK polarity: high; chipselect: active high */
+#define CONFIG_DEFAULT_SPI_MODE		(SPI_MODE_2 | SPI_CS_HIGH)
+
+/* Add PMIC RTC driver */
+#define CONFIG_RTC_MC13783		1
+
+
+/*******************************************************************************
  * Commands
  ******************************************************************************/
 

@@ -201,6 +219,8 @@
 #define CONFIG_CMD_I2C
 #define CONFIG_CMD_DTT
 #define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_SPI
+#define CONFIG_CMD_DATE
 
 
 /*******************************************************************************

index c704c41..abb8db0 100644
@@ -22,6 +22,7 @@
 
 #include <common.h>
 #include <asm/io.h>
+#include <spi.h>
 #include <asm/arch/mx31.h>
 #include <asm/arch/mx31-regs.h>
 

@@ -70,6 +71,132 @@ static void setup_iomux (void)
 	mx31_pad_ctl (PAD_CTL_CSPI2_MOSI, 0);
 }
 
+static int adjust_voltages (void)
+{
+	u32 reg;
+	u32 val;
+	static struct spi_slave *slave = NULL;
+
+	slave = spi_setup_slave(1, 0, 1000000,
+		SPI_MODE_2 | SPI_CS_HIGH);
+	if (!slave)
+		return -1;
+
+	if (spi_claim_bus(slave))
+		return -1;
+
+	/* Set PMIC arbitration switchers */
+	val = 0x000020;
+	reg = 0x14000000 | val | 0x80000000;
+	if (spi_xfer(slave, 32, (uchar *)&reg, (uchar *)&val,
+		SPI_XFER_BEGIN | SPI_XFER_END))
+		return -1;
+
+	/* Set PMIC regulator enable to 0x0 */
+	val = 0x000000;
+	reg = 0x20000000 | val | 0x80000000;
+	if (spi_xfer(slave, 32, (uchar *)&reg, (uchar *)&val,
+		SPI_XFER_BEGIN | SPI_XFER_END))
+		return -1;
+
+	/*
+	 * Set PMIC regulator setting 0
+	 *	VRFDIG = 1,8V / reset value = 1,875V
+	 *	VGEN   = 1,8V / reset value = 1,5V
+	 *	VDIG   = 1,3V / reset value = 1,5V
+	 */
+	val = 0x63cdc;
+	reg = 0x3c000000 | val | 0x80000000;
+	if (spi_xfer(slave, 32, (uchar *)&reg, (uchar *)&val,
+		SPI_XFER_BEGIN | SPI_XFER_END))
+		return -1;
+
+	/*
+	 * Set PMIC regulator mode 0 to 0x24924
+	 *	VAUDIO	= on
+	 *	VIOH	= off
+	 *	VIOLO	= on
+	 *	VDIG	= on
+	 *	VGEN	= on
+	 *	VRFDIG	= on
+	 *	VRFREF	= on
+	 *	VRFCP	= on
+	 */
+	val = 0x249241;
+	reg = 0x40000000 | val | 0x80000000;
+	if (spi_xfer(slave, 32, (uchar *)&reg, (uchar *)&val,
+		SPI_XFER_BEGIN | SPI_XFER_END))
+		return -1;
+
+	/*
+	 * Set PMIC regulator mode 1 to 0x0
+	 *	VSIM	= off
+	 *	VESIM	= off
+	 *	VCAM	= off
+	 *	VRFBG	= off
+	 *	VVIB	= off
+	 *	VRF1	= off
+	 *	VRF2	= off
+	 *	VMMC1	= off
+	 *	VMMC2	= off
+	 */
+	val = 0x0;
+	reg = 0x42000000 | val | 0x80000000;
+	if (spi_xfer(slave, 32, (uchar *)&reg, (uchar *)&val,
+		SPI_XFER_BEGIN | SPI_XFER_END))
+		return -1;
+
+	/*
+	 * FIXME: switcher settings 0 and 1.
+	 * Kernel hangs when unpacking itself.
+	 * Workaround:
+	 * Up to now CPU can operate at maximum allowed voltage 1.6 V.
+	 */
+	/*
+	 * Set PMIC switcher setting 0
+	 *	SW1A     = 1,2V / reset value = 1,6V
+	 *	SW1ADVS  = 1,6V / reset value = 1,6V
+	 *	SW1ASTBY = 1,2V / reset value = 1,6V
+	 */
+	/*
+	val = 0xc70c;
+	reg = 0x30000000 | val | 0x80000000;
+	if (spi_xfer(slave, 32, (uchar *)&reg, (uchar *)&val,
+		SPI_XFER_BEGIN | SPI_XFER_END))
+		return -1;
+	*/
+
+	/*
+	 * Set PMIC switcher setting 1
+	 *	SW1A     = 1,2V / reset value = 1,6V
+	 *	SW1ADVS  = 1,6V / reset value = 1,6V
+	 *	SW1ASTBY = 1,2V / reset value = 1,6V
+	 */
+	/*
+	val = 0xc70c;
+	reg = 0x32000000 | val | 0x80000000;
+	if (spi_xfer(slave, 32, (uchar *)&reg, (uchar *)&val,
+		SPI_XFER_BEGIN | SPI_XFER_END))
+		return -1;
+	*/
+
+	/*
+	 * Set PMIC switcher setting 5
+	 *	SW5 = 5V
+	 *	SW5 = off
+	 */
+	val = 0x021605;
+	reg = 0x3A000000 | val | 0x80000000;
+	if (spi_xfer(slave, 32, (uchar *)&reg, (uchar *)&val,
+		SPI_XFER_BEGIN | SPI_XFER_END))
+		return -1;
+
+	spi_release_bus(slave);
+	spi_free_slave(slave);
+
+	return 0;
+}
+
 int dram_init (void)
 {
 	gd->bd->bi_dram[0].start = PHYS_SDRAM_1;

@@ -112,3 +239,18 @@ int checkboard (void)
 	printf ("Board: TQMA31\n");
 	return 0;
 }
+
+int board_late_init(void)
+{
+	/*
+	 * Must call this function in late init stage, because the SPI driver,
+	 * required by this function, uses malloc(). The malloc space has not
+	 * been setup in the board_init() stage.
+	 */
+	if (adjust_voltages ()) {
+		printf ("Adjusting voltages failed!\n");
+		return -1;
+	}
+	return 0;
+}
+

index ac81a32..a174940 100644
@@ -299,6 +299,8 @@
  * Miscellaneous
  ******************************************************************************/
 
+#define BOARD_LATE_INIT
+
 /* Total available space for malloc in bytes */
 #define CFG_MALLOC_LEN			(CFG_ENV_SIZE + 128 * 1024)
 

index abb8db0..dd2bb0a 100644
@@ -69,6 +69,13 @@ static void setup_iomux (void)
 	mx31_pad_ctl (PAD_CTL_CSPI2_SPI_RDY, 0);
 	mx31_pad_ctl (PAD_CTL_CSPI2_MISO, 0);
 	mx31_pad_ctl (PAD_CTL_CSPI2_MOSI, 0);
+
+	/* Pins for IPU */
+	mx31_pad_ctl (PAD_CTL_FPSHIFT, PAD_CTL_IPP_PUE_PULL \
+					| PAD_CTL_IPP_PUS_100K_DN \
+					| PAD_CTL_IPP_HYS_STD \
+					| PAD_CTL_IPP_ODE_STD \
+					| PAD_CTL_IPP_SRE_FAST);
 }
 
 static int adjust_voltages (void)

index 4d661e8..407b2c6 100644
@@ -213,6 +213,7 @@
 #define	PAD_CTL_IO1_SHIFT		0
 #define	PAD_CTL_IO2_SHIFT		10
 #define	PAD_CTL_IO3_SHIFT		20
+#define PAD_CTL_FPSHIFT			((0x184 << 8) | PAD_CTL_IO1_SHIFT)
 #define PAD_CTL_CSPI2_SS2		((0x1F4 << 8) | PAD_CTL_IO3_SHIFT)
 #define PAD_CTL_CSPI2_SCLK		((0x1F4 << 8) | PAD_CTL_IO2_SHIFT)
 #define PAD_CTL_CSPI2_SPI_RDY		((0x1F4 << 8) | PAD_CTL_IO1_SHIFT)

index dd2bb0a..30584fe 100644
@@ -36,6 +36,12 @@ static void setup_chipselects (void)
 	__REG (CSCR_L(0)) = CSCR_L_OEA_10 | CSCR_L_EBWA_3 | CSCR_L_EBWN_3 \
 		| CSCR_L_EBC_ONLY_WA | CSCR_L_DSZ_16_MUM0 | CSCR_L_CSEN;
 
+	/* FPGA configuration flash on CS1 */
+	__REG (CSCR_U(1)) = CSCR_U_CNC_3 | CSCR_U_WSC_13 | CSCR_U_EDC_4;
+	__REG (CSCR_A(1)) = CSCR_A_RWA_2 | CSCR_A_RWN_2 | CSCR_A_LBN_2_MUM0;
+	__REG (CSCR_L(1)) = CSCR_L_OEA_10 | CSCR_L_EBWA_3 | CSCR_L_EBWN_3 \
+		| CSCR_L_EBC_ONLY_WA | CSCR_L_DSZ_16_MUM0 | CSCR_L_CSEN;
+
 	/* Ethernet controller on CS4 */
 	__REG (CSCR_U(4)) = CSCR_U_CNC_1 | CSCR_U_WSC_22 | CSCR_U_EDC_4;
 	__REG (CSCR_A(4)) = CSCR_A_RWA_2 | CSCR_A_RWN_15;

index 407b2c6..69d7614 100644
@@ -84,6 +84,7 @@
 #define CSCR_U_WSC_9		0x00000900
 #define CSCR_U_WSC_12		0x00000C00
 #define CSCR_U_WSC_22		0x00001600
+#define CSCR_U_WSC_13		0x00000D00
 #define CSCR_U_EDC_4		0x00000004
 #define CSCR_U_EDC_13		0x0000000D
 

index a174940..504cb57 100644
@@ -89,18 +89,21 @@
 #define CFG_FLASH_BASE			CS0_BASE
 
 /* Max number of memory banks */
-#define CFG_MAX_FLASH_BANKS		4
+#define CFG_MAX_FLASH_BANKS		5
 
 /*
  * Bank start addresses.
  * 4 x 32 MiB is the maximum for user and U-Boot code. Please adapt the list
  * as well as CFG_MAX_FLASH_BANKS to your TQM. Also consider dual die chips
  * or single die chips, e.g. one dual die chip represents two banks.
+ * The fifth bank is a separate chip for the FPGA configuration. It's
+ * controlled by chipselect 1.
  */
 #define CFG_FLASH_BANKS_LIST		{CFG_FLASH_BASE, 		\
 					CFG_FLASH_BASE + 32*1024*1024,	\
 					CFG_FLASH_BASE + 64*1024*1024,	\
-					CFG_FLASH_BASE + 96*1024*1024}
+					CFG_FLASH_BASE + 96*1024*1024,  \
+					CS1_BASE}
 
 /* Max number of sectors on one chip */
 #define CFG_MAX_FLASH_SECT		259

index 504cb57..e9e5d78 100644
@@ -275,6 +275,7 @@
 		"jtag=on "						\
 		"console=ttymxc0,115200\0"				\
 	"bootargs_nfs=setenv bootargs ${bootargs} "			\
+		"ethaddr=${ethaddr} "				        \
 		"root=/dev/nfs "					\
 		"ip=${ipaddr}:${serverip}:${gatewayip}:"		\
 			"${netmask}:${hostname}:${netdev}:off "		\