add support for uart_AO_B

PATCH New Martin Blumenstingl 3 participants 7 messages Jan 15, 2017 – Jan 18, 2017

Subsystems (4)

Device tree bindings GPIO Arm/Amlogic Meson SoC support Pin control

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Martin Blumenstingl

author reviewer

2017-01-15 22:20 UTC #0 lore raw

cover add support for uart_AO_B

This adds the uart_AO_B serial port and the related pinctrl nodes to meson-gx.

Due to a bug in the current GXBB and GXL/GXM pinctrl code uart_AO_B could not be used when uart_AO(_A) was enabled at the same time. The reason for this is that uart_AO_A and uart_AO_B were both trying to request the same pin as their RX pin (GPIOAO_1). uart_AO_B also requests a second pin for it's RX (GPIOAO_5), which does not make any sense.
Thus uart_AO_B is changed to only use GPIOAO_5 for RX and GPIOAO_4 for TX, which is also what the Amlogic reference kernel does.

Adding uart_AO_B is preparation work for adding support for the Khadas VIM and VIM Pro boards, as these are both exposing uart_AO_B on the pin-header.

Martin Blumenstingl (2):
pinctrl: meson: fix uart_ao_b for GXBB and GXL/GXM
ARM64: dts: meson-gx: add the missing uart_AO_B

 arch/arm64/boot/dts/amlogic/meson-gx.dtsi   | 8 ++++++++
 arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 7 +++++++
 arch/arm64/boot/dts/amlogic/meson-gxl.dtsi  | 7 +++++++
 drivers/pinctrl/meson/pinctrl-meson-gxbb.c  | 7 +++----
 drivers/pinctrl/meson/pinctrl-meson-gxl.c   | 7 +++----
 5 files changed, 28 insertions(+), 8 deletions(-)

Signature · 1 line

2.11.0

Martin Blumenstingl

author reviewer

2017-01-15 22:20 UTC #1 lore raw

PATCH 1/2 pinctrl: meson: fix uart_ao_b for GXBB and GXL/GXM

The GXBB and GXL/GXM pinctrl drivers had a configuration which conflicts with uart_ao_a. According to the GXBB ("S905") datasheet the AO UART functions are:
- GPIOAO_0: Func1 = UART_TX_AO_A (bit 12), Func2 = UART_TX_AO_B (bit 26)
- GPIOAO_1: Func1 = UART_RX_AO_A (bit 11), Func2 = UART_RX_AO_B (bit 25)
- GPIOAO_4: Func2 = UART_TX_AO_B (bit 24)
- GPIOAO_5: Func2 = UART_RX_AO_B (bit 25)

The existing definition for uart_AO_A already uses GPIOAO_0 and GPIOAO_1. The old definition of uart_AO_B however was broken, as it used GPIOAO_0 for TX (which would be fine) and two pins (GPIOAO_1 and GPIOAO_5) for RX (which does not make any sense).

This fixes the uart_AO_B configuration by moving it to GPIOAO_4 and GPIOAO_5 (it would be possible to use GPIOAO_0 and GPIOAO_1 in theory, but all existing hardware uses uart_AO_A there).
The fix for GXBB and GXL/GXM is identical since it seems that these specific pins are identical on both SoC variants.

Signed-off-by Martin Blumenstingl <[email protected]>

---
 drivers/pinctrl/meson/pinctrl-meson-gxbb.c | 7 +++----
 drivers/pinctrl/meson/pinctrl-meson-gxl.c  | 7 +++----
 2 files changed, 6 insertions(+), 8 deletions(-)

drivers/pinctrl/meson/pinctrl-meson-gxbb.c +3 -4

index c3928aa3fefa..e0bca4df2a2f 100644
@@ -253,9 +253,8 @@ static const unsigned int uart_tx_ao_a_pins[]	= { PIN(GPIOAO_0, 0) };
 static const unsigned int uart_rx_ao_a_pins[]	= { PIN(GPIOAO_1, 0) };
 static const unsigned int uart_cts_ao_a_pins[]	= { PIN(GPIOAO_2, 0) };
 static const unsigned int uart_rts_ao_a_pins[]	= { PIN(GPIOAO_3, 0) };
-static const unsigned int uart_tx_ao_b_pins[]	= { PIN(GPIOAO_0, 0) };
-static const unsigned int uart_rx_ao_b_pins[]	= { PIN(GPIOAO_1, 0),
-						    PIN(GPIOAO_5, 0) };
+static const unsigned int uart_tx_ao_b_pins[]	= { PIN(GPIOAO_4, 0) };
+static const unsigned int uart_rx_ao_b_pins[]	= { PIN(GPIOAO_5, 0) };
 static const unsigned int uart_cts_ao_b_pins[]	= { PIN(GPIOAO_2, 0) };
 static const unsigned int uart_rts_ao_b_pins[]	= { PIN(GPIOAO_3, 0) };

@@ -498,7 +497,7 @@ static struct meson_pmx_group meson_gxbb_aobus_groups[] = {
 	GPIO_GROUP(GPIOAO_13, 0),
 
 	/* bank AO */
-	GROUP(uart_tx_ao_b,	0,	26),
+	GROUP(uart_tx_ao_b,	0,	24),
 	GROUP(uart_rx_ao_b,	0,	25),
 	GROUP(uart_tx_ao_a,	0,	12),
 	GROUP(uart_rx_ao_a,	0,	11),

drivers/pinctrl/meson/pinctrl-meson-gxl.c +3 -4

index 25694f7094c7..b69743b07a1d 100644
@@ -214,9 +214,8 @@ static const unsigned int uart_tx_ao_a_pins[]	= { PIN(GPIOAO_0, 0) };
 static const unsigned int uart_rx_ao_a_pins[]	= { PIN(GPIOAO_1, 0) };
 static const unsigned int uart_cts_ao_a_pins[]	= { PIN(GPIOAO_2, 0) };
 static const unsigned int uart_rts_ao_a_pins[]	= { PIN(GPIOAO_3, 0) };
-static const unsigned int uart_tx_ao_b_pins[]	= { PIN(GPIOAO_0, 0) };
-static const unsigned int uart_rx_ao_b_pins[]	= { PIN(GPIOAO_1, 0),
-						    PIN(GPIOAO_5, 0) };
+static const unsigned int uart_tx_ao_b_pins[]	= { PIN(GPIOAO_4, 0) };
+static const unsigned int uart_rx_ao_b_pins[]	= { PIN(GPIOAO_5, 0) };
 static const unsigned int uart_cts_ao_b_pins[]	= { PIN(GPIOAO_2, 0) };
 static const unsigned int uart_rts_ao_b_pins[]	= { PIN(GPIOAO_3, 0) };

@@ -409,7 +408,7 @@ static struct meson_pmx_group meson_gxl_aobus_groups[] = {
 	GPIO_GROUP(GPIOAO_9, 0),
 
 	/* bank AO */
-	GROUP(uart_tx_ao_b,	0,	26),
+	GROUP(uart_tx_ao_b,	0,	24),
 	GROUP(uart_rx_ao_b,	0,	25),
 	GROUP(uart_tx_ao_a,	0,	12),
 	GROUP(uart_rx_ao_a,	0,	11),

Signature · 1 line

2.11.0

Linus Walleij

2017-01-18 10:21 UTC #2 lore raw

PATCH 1/2 pinctrl: meson: fix uart_ao_b for GXBB and GXL/GXM

Quoted 13 lines · Martin Blumenstingl

The GXBB and GXL/GXM pinctrl drivers had a configuration which conflicts with uart_ao_a. According to the GXBB ("S905") datasheet the AO UART functions are:
- GPIOAO_0: Func1 = UART_TX_AO_A (bit 12), Func2 = UART_TX_AO_B (bit 26)
- GPIOAO_1: Func1 = UART_RX_AO_A (bit 11), Func2 = UART_RX_AO_B (bit 25)
- GPIOAO_4: Func2 = UART_TX_AO_B (bit 24)
- GPIOAO_5: Func2 = UART_RX_AO_B (bit 25)
The existing definition for uart_AO_A already uses GPIOAO_0 and GPIOAO_1. The old definition of uart_AO_B however was broken, as it used GPIOAO_0 for TX (which would be fine) and two pins (GPIOAO_1 and GPIOAO_5) for RX (which does not make any sense).

Quoted 7 lines

This fixes the uart_AO_B configuration by moving it to GPIOAO_4 and GPIOAO_5 (it would be possible to use GPIOAO_0 and GPIOAO_1 in theory, but all existing hardware uses uart_AO_A there).
The fix for GXBB and GXL/GXM is identical since it seems that these specific pins are identical on both SoC variants.
Signed-off-by Martin Blumenstingl <[email protected]>

Patch applied for fixes.

Yours,
Linus Walleij

Kevin Hilman

maintainer

2017-01-18 21:40 UTC #3 lore raw

PATCH 1/2 pinctrl: meson: fix uart_ao_b for GXBB and GXL/GXM

In reply to Martin Blumenstingl

Quoted 13 lines · Martin Blumenstingl

The GXBB and GXL/GXM pinctrl drivers had a configuration which conflicts with uart_ao_a. According to the GXBB ("S905") datasheet the AO UART functions are:
- GPIOAO_0: Func1 = UART_TX_AO_A (bit 12), Func2 = UART_TX_AO_B (bit 26)
- GPIOAO_1: Func1 = UART_RX_AO_A (bit 11), Func2 = UART_RX_AO_B (bit 25)
- GPIOAO_4: Func2 = UART_TX_AO_B (bit 24)
- GPIOAO_5: Func2 = UART_RX_AO_B (bit 25)
The existing definition for uart_AO_A already uses GPIOAO_0 and GPIOAO_1. The old definition of uart_AO_B however was broken, as it used GPIOAO_0 for TX (which would be fine) and two pins (GPIOAO_1 and GPIOAO_5) for RX (which does not make any sense).

Quoted 7 lines

This fixes the uart_AO_B configuration by moving it to GPIOAO_4 and GPIOAO_5 (it would be possible to use GPIOAO_0 and GPIOAO_1 in theory, but all existing hardware uses uart_AO_A there).
The fix for GXBB and GXL/GXM is identical since it seems that these specific pins are identical on both SoC variants.
Signed-off-by Martin Blumenstingl <[email protected]>

Reviewed-by Kevin Hilman <[email protected]>

Quoted 55 lines

---
 drivers/pinctrl/meson/pinctrl-meson-gxbb.c | 7 +++----
 drivers/pinctrl/meson/pinctrl-meson-gxl.c  | 7 +++----
 2 files changed, 6 insertions(+), 8 deletions(-)

drivers/pinctrl/meson/pinctrl-meson-gxbb.c +3 -4

index c3928aa3fefa..e0bca4df2a2f 100644
@@ -253,9 +253,8 @@ static const unsigned int uart_tx_ao_a_pins[]	= { PIN(GPIOAO_0, 0) };
 static const unsigned int uart_rx_ao_a_pins[]	= { PIN(GPIOAO_1, 0) };
 static const unsigned int uart_cts_ao_a_pins[]	= { PIN(GPIOAO_2, 0) };
 static const unsigned int uart_rts_ao_a_pins[]	= { PIN(GPIOAO_3, 0) };
-static const unsigned int uart_tx_ao_b_pins[]	= { PIN(GPIOAO_0, 0) };
-static const unsigned int uart_rx_ao_b_pins[]	= { PIN(GPIOAO_1, 0),
-						    PIN(GPIOAO_5, 0) };
+static const unsigned int uart_tx_ao_b_pins[]	= { PIN(GPIOAO_4, 0) };
+static const unsigned int uart_rx_ao_b_pins[]	= { PIN(GPIOAO_5, 0) };
 static const unsigned int uart_cts_ao_b_pins[]	= { PIN(GPIOAO_2, 0) };
 static const unsigned int uart_rts_ao_b_pins[]	= { PIN(GPIOAO_3, 0) };

@@ -498,7 +497,7 @@ static struct meson_pmx_group meson_gxbb_aobus_groups[] = {
 	GPIO_GROUP(GPIOAO_13, 0),
 
 	/* bank AO */
-	GROUP(uart_tx_ao_b,	0,	26),
+	GROUP(uart_tx_ao_b,	0,	24),
 	GROUP(uart_rx_ao_b,	0,	25),
 	GROUP(uart_tx_ao_a,	0,	12),
 	GROUP(uart_rx_ao_a,	0,	11),

drivers/pinctrl/meson/pinctrl-meson-gxl.c +3 -4

index 25694f7094c7..b69743b07a1d 100644
@@ -214,9 +214,8 @@ static const unsigned int uart_tx_ao_a_pins[]	= { PIN(GPIOAO_0, 0) };
 static const unsigned int uart_rx_ao_a_pins[]	= { PIN(GPIOAO_1, 0) };
 static const unsigned int uart_cts_ao_a_pins[]	= { PIN(GPIOAO_2, 0) };
 static const unsigned int uart_rts_ao_a_pins[]	= { PIN(GPIOAO_3, 0) };
-static const unsigned int uart_tx_ao_b_pins[]	= { PIN(GPIOAO_0, 0) };
-static const unsigned int uart_rx_ao_b_pins[]	= { PIN(GPIOAO_1, 0),
-						    PIN(GPIOAO_5, 0) };
+static const unsigned int uart_tx_ao_b_pins[]	= { PIN(GPIOAO_4, 0) };
+static const unsigned int uart_rx_ao_b_pins[]	= { PIN(GPIOAO_5, 0) };
 static const unsigned int uart_cts_ao_b_pins[]	= { PIN(GPIOAO_2, 0) };
 static const unsigned int uart_rts_ao_b_pins[]	= { PIN(GPIOAO_3, 0) };

@@ -409,7 +408,7 @@ static struct meson_pmx_group meson_gxl_aobus_groups[] = {
 	GPIO_GROUP(GPIOAO_9, 0),
 
 	/* bank AO */
-	GROUP(uart_tx_ao_b,	0,	26),
+	GROUP(uart_tx_ao_b,	0,	24),
 	GROUP(uart_rx_ao_b,	0,	25),
 	GROUP(uart_tx_ao_a,	0,	12),
 	GROUP(uart_rx_ao_a,	0,	11),

Martin Blumenstingl

author reviewer

2017-01-15 22:20 UTC #4 lore raw

PATCH 2/2 ARM64: dts: meson-gx: add the missing uart_AO_B

In reply to Martin Blumenstingl

This adds the missing node for the uart_AO_B port to the meson-gx.dtsi (as this is supported by GXBB, GXL and GXM) along with the required pinctrl pins. This is required as some boards are using it (the boards from the Khadas VIM series for example have it exposed on the pin headers).

Signed-off-by Martin Blumenstingl <[email protected]>

---
 arch/arm64/boot/dts/amlogic/meson-gx.dtsi   | 8 ++++++++
 arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 7 +++++++
 arch/arm64/boot/dts/amlogic/meson-gxl.dtsi  | 7 +++++++
 3 files changed, 22 insertions(+)

arch/arm64/boot/dts/amlogic/meson-gx.dtsi +8 -0

index cddad8c795ec..5ece505dca71 100644
@@ -324,6 +324,14 @@
 				status = "disabled";
 			};
 
+			uart_AO_B: serial at 4e0 {
+				compatible = "amlogic,meson-uart";
+				reg = <0x0 0x004e0 0x0 0x14>;
+				interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
+				clocks = <&xtal>;
+				status = "disabled";
+			};
+
 			ir: ir at 580 {
 				compatible = "amlogic,meson-gxbb-ir";
 				reg = <0x0 0x00580 0x0 0x40>;

arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi +7 -0

index 5d686334f692..474435e21759 100644
@@ -138,6 +138,13 @@
 			};
 		};
 
+		uart_ao_b_pins: uart_ao_b {
+			mux {
+				groups = "uart_tx_ao_b", "uart_rx_ao_b";
+				function = "uart_ao_b";
+			};
+		};
+
 		remote_input_ao_pins: remote_input_ao {
 			mux {
 				groups = "remote_input_ao";

arch/arm64/boot/dts/amlogic/meson-gxl.dtsi +7 -0

index bb2842f8a08f..53ed7a5f50ab 100644
@@ -82,6 +82,13 @@
 			};
 		};
 
+		uart_ao_b_pins: uart_ao_b {
+			mux {
+				groups = "uart_tx_ao_b", "uart_rx_ao_b";
+				function = "uart_ao_b";
+			};
+		};
+
 		remote_input_ao_pins: remote_input_ao {
 			mux {
 				groups = "remote_input_ao";

Signature · 1 line

2.11.0

Linus Walleij

2017-01-18 10:22 UTC #5 lore raw

PATCH 2/2 ARM64: dts: meson-gx: add the missing uart_AO_B

Quoted 7 lines · Martin Blumenstingl

This adds the missing node for the uart_AO_B port to the meson-gx.dtsi (as this is supported by GXBB, GXL and GXM) along with the required pinctrl pins. This is required as some boards are using it (the boards from the Khadas VIM series for example have it exposed on the pin headers).
Signed-off-by Martin Blumenstingl <[email protected]>

Acked-by Linus Walleij <[email protected]>

Please funnel this through the apropriate ARM SoC-feed tree.

Yours,
Linus Walleij

Kevin Hilman

maintainer Applied

2017-01-18 21:43 UTC #6 lore raw

PATCH 2/2 ARM64: dts: meson-gx: add the missing uart_AO_B

In reply to Martin Blumenstingl

Quoted 7 lines · Martin Blumenstingl

This adds the missing node for the uart_AO_B port to the meson-gx.dtsi (as this is supported by GXBB, GXL and GXM) along with the required pinctrl pins. This is required as some boards are using it (the boards from the Khadas VIM series for example have it exposed on the pin headers).
Signed-off-by Martin Blumenstingl <[email protected]>

Applied to v4.11/dt64.

Kevin