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CNS3xxx: Cosmetic: Fix misc register usage

PATCH New Krzysztof Hałasa 1 participant 1 message May 10, 2018

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Arm (32-bit) Arm sub-architectures
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Krzysztof Hałasa

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PATCH 1/1 CNS3xxx: Cosmetic: Fix misc register usage

Signed-off-by Krzysztof Ha?asa <[email protected]>
arch/arm/mach-cns3xxx/core.c +1 -1
@@ -395,7 +395,7 @@ static void __init cns3xxx_init(void)
 
 	dn = of_find_compatible_node(NULL, NULL, "cavium,cns3420-sdhci");
 	if (of_device_is_available(dn)) {
-		u32 __iomem *gpioa = IOMEM(CNS3XXX_MISC_BASE_VIRT + 0x0014);
+		u32 __iomem *gpioa = IOMEM(MISC_GPIOA_PIN_ENABLE_REG);
 		u32 gpioa_pins = __raw_readl(gpioa);
 	
 		/* MMC/SD pins share with GPIOA */
arch/arm/mach-cns3xxx/devices.c +1 -1
index 7da78a2451f1..daafbe764a96 100644
@@ -97,7 +97,7 @@ static struct platform_device cns3xxx_sdhci_pdev = {
 
 void __init cns3xxx_sdhci_init(void)
 {
-	u32 __iomem *gpioa = IOMEM(CNS3XXX_MISC_BASE_VIRT + 0x0014);
+	u32 __iomem *gpioa = IOMEM(MISC_GPIOA_PIN_ENABLE_REG);
 	u32 gpioa_pins = __raw_readl(gpioa);
 
 	/* MMC/SD pins share with GPIOA */
Signature · 4 lines
Krzysztof Halasa

Industrial Research Institute for Automation and Measurements PIAP
Al. Jerozolimskie 202, 02-486 Warsaw, Poland