CPU/cache detection wrong

DISCUSSION Alexander Hoogerhuis 4 participants 8 messages Sep 30, 2002 – Oct 1, 2002

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Alexander Hoogerhuis

author

2002-09-30 15:01 UTC #0 lore raw

Accroding to my kernel, this is what i got:

CPU: Before vendor init, caps: 3febf9ff 00000000 00000000, vendor = 0
CPU: L1 I cache: 0K, L1 D cache: 8K
CPU: L2 cache: 512K
CPU: After vendor init, caps: 3febf9ff 00000000 00000000 00000000 Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#0.

CPU:     After generic, caps: 3febf9ff 00000000 00000000 00000000
CPU:             Common caps: 3febf9ff 00000000 00000000 00000000
CPU: Intel(R) Pentium(R) 4 Mobile CPU 1.70GHz stepping 04

Enabling fast FPU save and restore... done. Enabling unmasked SIMD FPU exception support... done. Checking 'hlt' instruction... OK.

The machine is a Comapq Evo n800c with a 1.7GHz P4-M in it, and according to the BIOS I've got 16kb/512Kb L1/L2-cache. Accroding to the 2.4.20-pre7-ac3-kernel. It's been like this at least since 2.4.19-pre4 or so.

mvh,
A

Signature · 3 lines

Alexander Hoogerhuis                               | [email protected]
CCNP - CCDP - MCNE - CCSE                          | +47 908 21 485
"You have zero privacy anyway. Get over it."  --Scott McNealy

Alan Cox

2002-09-30 16:22 UTC #1 lore raw

Quoted 9 lines · Alexander Hoogerhuis

CPU: Intel(R) Pentium(R) 4 Mobile CPU 1.70GHz stepping 04 Enabling fast FPU save and restore... done. Enabling unmasked SIMD FPU exception support... done. Checking 'hlt' instruction... OK.
The machine is a Comapq Evo n800c with a 1.7GHz P4-M in it, and according to the BIOS I've got 16kb/512Kb L1/L2-cache. Accroding to the 2.4.20-pre7-ac3-kernel. It's been like this at least since 2.4.19-pre4 or so.

Can you stick a printk in arch/i386/kernel/setup.c in the function init_intel

Just before:

        /* look up this descriptor in the table */

stick

        printk("Cache info byte: %02X\n", des);

that will dump the cache info out of the CPU as the kernel scans it and should let us find the error in the table.

Alexander Hoogerhuis

author

2002-09-30 17:38 UTC #2 lore raw

Quoted 15 lines · Alan Cox

Quoted 9 lines · Alexander Hoogerhuis
CPU: Intel(R) Pentium(R) 4 Mobile CPU 1.70GHz stepping 04 Enabling fast FPU save and restore... done. Enabling unmasked SIMD FPU exception support... done. Checking 'hlt' instruction... OK.
The machine is a Comapq Evo n800c with a 1.7GHz P4-M in it, and according to the BIOS I've got 16kb/512Kb L1/L2-cache. Accroding to the 2.4.20-pre7-ac3-kernel. It's been like this at least since 2.4.19-pre4 or so.
Can you stick a printk in arch/i386/kernel/setup.c in the function init_intel
Just before:

Quoted 9 lines

        /* look up this descriptor in the table */
stick
        printk("Cache info byte: %02X\n", des);
that will dump the cache info out of the CPU as the kernel scans it and should let us find the error in the table.

And the jury says:

PU: Before vendor init, caps: 3febf9ff 00000000 00000000, vendor = 0 Cache info byte: 50
Cache info byte: 5B
Cache info byte: 66
Cache info byte: 00
Cache info byte: 00
Cache info byte: 00
Cache info byte: 00
Cache info byte: 00
Cache info byte: 00
Cache info byte: 00
Cache info byte: 00
Cache info byte: 40
Cache info byte: 70
Cache info byte: 7B
Cache info byte: 00
CPU: L1 I cache: 0K, L1 D cache: 8K
CPU: L2 cache: 512K
CPU: After vendor init, caps: 3febf9ff 00000000 00000000 00000000

Let me know if you need more info :)

mvh,
A

Signature · 3 lines

Alexander Hoogerhuis                               | [email protected]
CCNP - CCDP - MCNE - CCSE                          | +47 908 21 485
"You have zero privacy anyway. Get over it."  --Scott McNealy

Dave Jones

2002-09-30 22:07 UTC #3 lore raw

Quoted 2 lines · Alexander Hoogerhuis

PU: Before vendor init, caps: 3febf9ff 00000000 00000000, vendor = 0 Cache info byte: 50

Instruction TLB (ignored)

Quoted 1 line

Cache info byte: 5B

Data TLB (ignored)

Quoted 1 line

Cache info byte: 66

8K L1 data cache

Quoted 8 lines

Cache info byte: 00
Cache info byte: 00
Cache info byte: 00
Cache info byte: 00
Cache info byte: 00
Cache info byte: 00
Cache info byte: 00
Cache info byte: 00

Null

Quoted 1 line

Cache info byte: 40

No 3rd level cache.

Quoted 1 line

Cache info byte: 70

12K-uops trace cache

Quoted 1 line

Cache info byte: 7B

512K L2 cache

Quoted 1 line

Cache info byte: 00

Null.

Quoted 2 lines

CPU: L1 I cache: 0K, L1 D cache: 8K
CPU: L2 cache: 512K

So all is correct, except for the missing trace cache entries.

Patch below adds several missing descriptors, fixes up
an errata workaround, and adds reporting for the trace cache.
I've no Intel hardware to test this code with, so if people can make sure I've not broken anything, that'd be good (I hate touching this code).

Alex, with this patch, you should see..

CPU: Trace cache: 12K uops, L1 D cache: 8K
CPU: L2 cache: 512K

Confirmed ?

Dave

arch/i386/kernel/setup.c +30 ~~-14~~

diff -urpN --exclude-from=/home/davej/.exclude linux-2.4.20-pre8/arch/i386/kernel/setup.c linux-2.4.20-pre8-leakfix/arch/i386/kernel/setup.c
@@ -1256,15 +1256,6 @@ static void __init display_cacheinfo(str
 			l2size = 256;
 	}
 
-	/* Intel PIII Tualatin. This comes in two flavours.
-	 * One has 256kb of cache, the other 512. We have no way
-	 * to determine which, so we use a boottime override
-	 * for the 512kb model, and assume 256 otherwise.
-	 */
-	if ((c->x86_vendor == X86_VENDOR_INTEL) && (c->x86 == 6) &&
-		(c->x86_model == 11) && (l2size == 0))
-		l2size = 256;
-
 	/* VIA C3 CPUs (670-68F) need further shifting. */
 	if (c->x86_vendor == X86_VENDOR_CENTAUR && (c->x86 == 6) &&
 		((c->x86_model == 7) || (c->x86_model == 8))) {

@@ -2180,6 +2171,7 @@ extern void trap_init_f00f_bug(void);
 #define LVL_1_DATA      2
 #define LVL_2           3
 #define LVL_3           4
+#define LVL_TRACE       5
 
 struct _cache_table
 {

@@ -2199,6 +2191,8 @@ static struct _cache_table cache_table[]
 	{ 0x23, LVL_3,      1024 },
 	{ 0x25, LVL_3,      2048 },
 	{ 0x29, LVL_3,      4096 },
+	{ 0x39, LVL_2,      128 },
+	{ 0x3C, LVL_2,      256 },
 	{ 0x41, LVL_2,      128 },
 	{ 0x42, LVL_2,      256 },
 	{ 0x43, LVL_2,      512 },

@@ -2207,11 +2201,15 @@ static struct _cache_table cache_table[]
 	{ 0x66, LVL_1_DATA, 8 },
 	{ 0x67, LVL_1_DATA, 16 },
 	{ 0x68, LVL_1_DATA, 32 },
+	{ 0x70, LVL_TRACE,  12 },
+	{ 0x71, LVL_TRACE,  16 },
+	{ 0x72, LVL_TRACE,  32 },
 	{ 0x79, LVL_2,      128 },
 	{ 0x7A, LVL_2,      256 },
 	{ 0x7B, LVL_2,      512 },
 	{ 0x7C, LVL_2,      1024 },
 	{ 0x82, LVL_2,      256 },
+	{ 0x83, LVL_2,      512 },
 	{ 0x84, LVL_2,      1024 },
 	{ 0x85, LVL_2,      2048 },
 	{ 0x00, 0, 0}

@@ -2219,7 +2217,7 @@ static struct _cache_table cache_table[]
 
 static void __init init_intel(struct cpuinfo_x86 *c)
 {
-	unsigned int l1i = 0, l1d = 0, l2 = 0, l3 = 0; /* Cache sizes */
+	unsigned int trace = 0, l1i = 0, l1d = 0, l2 = 0, l3 = 0; /* Cache sizes */
 	char *p = NULL;
 #ifndef CONFIG_X86_F00F_WORKS_OK
 	static int f00f_workaround_enabled = 0;

@@ -2279,8 +2277,10 @@ static void __init init_intel(struct cpu
 						case LVL_3:
 							l3 += cache_table[k].size;
 							break;
+						case LVL_TRACE:
+							trace += cache_table[k].size;
+							break;
 						}
-
 						break;
 					}

@@ -2288,9 +2288,25 @@ static void __init init_intel(struct cpu
 				}
 			}
 		}
-		if ( l1i || l1d )
-			printk(KERN_INFO "CPU: L1 I cache: %dK, L1 D cache: %dK\n",
-			       l1i, l1d);
+
+		/* Intel PIII Tualatin. This comes in two flavours.
+		 * One has 256kb of cache, the other 512. We have no way
+		 * to determine which, so we use a boottime override
+		 * for the 512kb model, and assume 256 otherwise.
+		 */
+		if ((c->x86 == 6) && (c->x86_model == 11) && (l2 == 0))
+			l2 = 256;
+		/* Allow user to override all this if necessary. */
+		if (cachesize_override != -1)
+			l2 = cachesize_override;
+
+		if ( trace )
+			printk (KERN_INFO "CPU: Trace cache: %dK uops", trace);
+		else if ( l1i )
+			printk (KERN_INFO "CPU: L1 I cache: %dK", l1i);
+		if ( l1d )
+			printk(", L1 D cache: %dK\n", l1d);
+
 		if ( l2 )
 			printk(KERN_INFO "CPU: L2 cache: %dK\n", l2);
 		if ( l3 )

Signature · 1 line

| Dave Jones.        http://www.codemonkey.org.uk

Alexander Hoogerhuis

author

2002-10-01 07:16 UTC #4 lore raw

Quoted 34 lines · Dave Jones

Quoted 2 lines · Alexander Hoogerhuis
PU: Before vendor init, caps: 3febf9ff 00000000 00000000, vendor = 0 Cache info byte: 50
Instruction TLB (ignored)
Quoted 1 line
Cache info byte: 5B
Data TLB (ignored)
Quoted 1 line
Cache info byte: 66
8K L1 data cache
Quoted 8 lines
Cache info byte: 00
Cache info byte: 00
Cache info byte: 00
Cache info byte: 00
Cache info byte: 00
Cache info byte: 00
Cache info byte: 00
Cache info byte: 00
Null
Quoted 1 line
Cache info byte: 40
No 3rd level cache.
Quoted 1 line
Cache info byte: 70
12K-uops trace cache

Quoted 11 lines

Quoted 1 line
Cache info byte: 7B
512K L2 cache
Quoted 1 line
Cache info byte: 00
Null.
Quoted 2 lines
CPU: L1 I cache: 0K, L1 D cache: 8K
CPU: L2 cache: 512K

Here we go:

CPU: Trace cache: 12K uops, L1 D cache: 8K
CPU: L2 cache: 512K

But my BIOS still say I should have 8Kb/8Kb I/D L1 cache... oh well. I'm sure Alan Cox would just write it up as marketing, since thats about how reliable a BIOS is :)

ttfn,
A

Signature · 3 lines

Alexander Hoogerhuis                               | [email protected]
CCNP - CCDP - MCNE - CCSE                          | +47 908 21 485
"You have zero privacy anyway. Get over it."  --Scott McNealy

Dave Jones

2002-10-01 10:58 UTC #5 lore raw

Quoted 48 lines · Alexander Hoogerhuis

Quoted 34 lines · Dave Jones
Quoted 2 lines · Alexander Hoogerhuis
PU: Before vendor init, caps: 3febf9ff 00000000 00000000, vendor = 0 Cache info byte: 50
Instruction TLB (ignored)
Quoted 1 line
Cache info byte: 5B
Data TLB (ignored)
Quoted 1 line
Cache info byte: 66
8K L1 data cache
Quoted 8 lines
Cache info byte: 00
Cache info byte: 00
Cache info byte: 00
Cache info byte: 00
Cache info byte: 00
Cache info byte: 00
Cache info byte: 00
Cache info byte: 00
Null
Quoted 1 line
Cache info byte: 40
No 3rd level cache.
Quoted 1 line
Cache info byte: 70
12K-uops trace cache
Quoted 11 lines
Quoted 1 line
Cache info byte: 7B
512K L2 cache
Quoted 1 line
Cache info byte: 00
Null.
Quoted 2 lines
CPU: L1 I cache: 0K, L1 D cache: 8K
CPU: L2 cache: 512K

Quoted 8 lines

Here we go:
CPU: Trace cache: 12K uops, L1 D cache: 8K
CPU: L2 cache: 512K
But my BIOS still say I should have 8Kb/8Kb I/D L1 cache... oh well. I'm sure Alan Cox would just write it up as marketing, since thats about how reliable a BIOS is :)

Hmm, can a P4 have a trace cache AND an L1 I cache ? I thought they were exclusive, which is why the code doesn't take this into account. Easily fixed if so though..

Dave

Signature · 1 line

| Dave Jones.        http://www.codemonkey.org.uk

Alexander Hoogerhuis

author

2002-10-01 15:26 UTC #6 lore raw

Quoted 6 lines · Dave Jones

Quoted 5 lines · Alexander Hoogerhuis
Here we go:
CPU: Trace cache: 12K uops, L1 D cache: 8K
CPU: L2 cache: 512K

Quoted 8 lines

Quoted 3 lines
But my BIOS still say I should have 8Kb/8Kb I/D L1 cache... oh well. I'm sure Alan Cox would just write it up as marketing, since thats about how reliable a BIOS is :)
Hmm, can a P4 have a trace cache AND an L1 I cache ? I thought they were exclusive, which is why the code doesn't take this into account. Easily fixed if so though..

I don't know the gory details of it, but my BIOS claims I got 8/8, but I'm deep enough in it now to start taking the 5th amendment on the details here :)

ttfn,
A

Signature · 3 lines

Alexander Hoogerhuis                               | [email protected]
CCNP - CCDP - MCNE - CCSE                          | +47 908 21 485
"You have zero privacy anyway. Get over it."  --Scott McNealy

Vojtech Pavlik

2002-10-01 16:56 UTC #7 lore raw

Quoted 12 lines · Alexander Hoogerhuis

Quoted 10 lines · Dave Jones
Quoted 8 lines · Alexander Hoogerhuis
Here we go:
CPU: Trace cache: 12K uops, L1 D cache: 8K
CPU: L2 cache: 512K
But my BIOS still say I should have 8Kb/8Kb I/D L1 cache... oh well. I'm sure Alan Cox would just write it up as marketing, since thats about how reliable a BIOS is :)

Quoted 8 lines

Quoted 4 lines
Hmm, can a P4 have a trace cache AND an L1 I cache ? I thought they were exclusive, which is why the code doesn't take this into account. Easily fixed if so though..
I don't know the gory details of it, but my BIOS claims I got 8/8, but I'm deep enough in it now to start taking the 5th amendment on the details here :)

12k of trace cache and 8k of I-cache are more or less equivalent - trace cache is less effective because it has decoded uops, while i-cache has encoded instructions, which take up less space.

Signature · 2 lines

Vojtech Pavlik
SuSE Labs