2.5.68 small generic HDLC update

@@ -217,15 +217,9 @@
 	int io = port->card->io;
 	u8 mcr = inb(io + N2_MCR) | (port->phy_node ? TX422_PORT1:TX422_PORT0);
 
-
-	if (!try_module_get(THIS_MODULE))
-		return -EFAULT;	/* rmmod in progress */
-
 	int result = hdlc_open(hdlc);
-	if (result) {
+	if (result)
 		return result;
-		module_put(THIS_MODULE);
-	}
 
 	mcr &= port->phy_node ? ~DTR_PORT1 : ~DTR_PORT0; /* set DTR ON */
 	outb(mcr, io + N2_MCR);

@@ -250,7 +244,6 @@
 	mcr |= port->phy_node ? DTR_PORT1 : DTR_PORT0; /* set DTR OFF */
 	outb(mcr, io + N2_MCR);
 	hdlc_close(hdlc);
-	module_put(THIS_MODULE);
 	return 0;
 }
 

@@ -450,6 +443,7 @@
 			port->log_node = 1;
 
 		spin_lock_init(&port->lock);
+		SET_MODULE_OWNER(dev);
 		dev->irq = irq;
 		dev->mem_start = winbase;
 		dev->mem_end = winbase + USE_WINDOWSIZE-1;

@@ -156,14 +156,9 @@
 	hdlc_device *hdlc = dev_to_hdlc(dev);
 	port_t *port = hdlc_to_port(hdlc);
 
-	if (!try_module_get(THIS_MODULE))
-		return -EFAULT;	/* rmmod in progress */
-
 	int result = hdlc_open(hdlc);
-	if (result) {
+	if (result)
 		return result;
-		module_put(THIS_MODULE);
-	}
 
 	writeb(1, port->win0base + C101_DTR);
 	sca_out(0, MSCI1_OFFSET + CTL, port); /* RTS uses ch#2 output */

@@ -182,7 +177,6 @@
 	writeb(0, port->win0base + C101_DTR);
 	sca_out(CTL_NORTS, MSCI1_OFFSET + CTL, port);
 	hdlc_close(hdlc);
-	module_put(THIS_MODULE);
 	return 0;
 }
 

@@ -318,6 +312,7 @@
 	dev = hdlc_to_dev(&card->hdlc);
 
 	spin_lock_init(&card->lock);
+	SET_MODULE_OWNER(dev);
 	dev->irq = irq;
 	dev->mem_start = winbase;
 	dev->mem_end = winbase + C101_MAPPED_RAM_SIZE - 1;