(2.4.21-bjorn-bk) ivt rearrangement and sn2-specific boot-time replacement of alternate d-tl

Hi,

This patch is against the linux-ia64-2.4 bk tree (as of a few minutes ago). It should apply cleanly to almost any recent 2.4.x tree though.

Like the previous patch this is as much for discussion as inclusion.

As previously mentioned, Altix/SN2 has mixed cachability in the granule containing the PAL[1]. For this reason we use a different alternate-dtlb-miss handler than the mainline kernel.

Rather than force everyone to deal with this I've opted for a small rearrangement and code which allows the platform specific code to boot-time replace the alternate d-tlb code with it's own version.

Other than the small rearrangement of arch/ia64/kernel/ivt.S this should uninteresting to non-Altix platforms.

Flame away!

--cw

[1] This is only part of it. The PROM reserve space in granule-0 for uncahable access using by the fetchop driver.

 kernel/ivt.S       |   89 ++++++++++++++++++++++-----------------
 sn/kernel/Makefile |    1
 sn/kernel/setup.c  |   73 ++++++++++++++++++++++++++++++++
 sn/kernel/sn_ivt.S |   96 +++++++++++++++++++++++++++++++++++++++++++
 4 files changed, 220 insertions(+), 39 deletions(-)

# This is a BitKeeper generated patch for the following project:
# Project Name: Linux kernel tree
# This patch format is intended for GNU patch command version 2.5 or higher. # This patch includes the following deltas:
# ChangeSet 1.1148 -> 1.1149
# arch/ia64/kernel/ivt.S 1.8 -> 1.9
# arch/ia64/sn/kernel/Makefile 1.4 -> 1.5
# arch/ia64/sn/kernel/setup.c 1.8 -> 1.9
# (new) -> 1.1 arch/ia64/sn/kernel/sn_ivt.S
#
# The following is the BitKeeper ChangeSet Log
# --------------------------------------------
# 03/07/15 [email protected] 1.1149
# Code to dynamically (boot-time) replace the alternate d-tlb miss handler when running

# on SN2 hardware.  This replacement handler has semantics compatible with SN2 low-memory
# layout as dictated by the PROM.
# --------------------------------------------
#
diff -Nru a/arch/ia64/kernel/ivt.S b/arch/ia64/kernel/ivt.S
--- a/arch/ia64/kernel/ivt.S	Tue Jul 15 18:53:16 2003
+++ b/arch/ia64/kernel/ivt.S	Tue Jul 15 18:53:16 2003
@@ -171,7 +171,7 @@
 	;;
 (p10)	itc.i r18				// insert the instruction TLB entry
 (p11)	itc.d r18				// insert the data TLB entry
-(p6)	br.cond.spnt.many page_fault		// handle bad address/page not present (page fault)
+(p6)	br.cond.spnt.many ia64_ivt_page_fault  	// handle bad address/page not present (page fault)
 	mov cr.ifa=r22

#ifdef CONFIG_HUGETLB_PAGE
@@ -231,7 +231,7 @@
;;
mov b0=r29
tbit.z p6,p0=r18,_PAGE_P_BIT // page present bit cleared?
-(p6) br.cond.spnt page_fault
+(p6) br.cond.spnt ia64_ivt_page_fault
;;
itc.i r18
;;
@@ -269,7 +269,7 @@
;;
mov b0=r29
tbit.z p6,p0=r18,_PAGE_P_BIT // page present bit cleared?
-(p6) br.cond.spnt page_fault
+(p6) br.cond.spnt ia64_ivt_page_fault
;;
itc.d r18
;;
@@ -316,7 +316,7 @@
or r19=r17,r19 // insert PTE control bits into r19
;;
or r19=r19,r18 // set bit 4 (uncached) if the access was to region 6
-(p8) br.cond.spnt page_fault
+(p8) br.cond.spnt ia64_ivt_page_fault
;;
itc.i r19 // insert the TLB entry
mov pr=r31,-1
@@ -326,6 +326,7 @@
.align 1024
///////////////////////////////////////////////////////////////////////////////////////// // 0x1000 Entry 4 (size 64 bundles) Alt DTLB (7,46)
+ .global alt_dtlb_miss
ENTRY(alt_dtlb_miss)
DBG_FAULT(4)
mov r16=cr.ifa // get address that caused the TLB miss
@@ -356,7 +357,7 @@
andcm r18=0x10,r18 // bit 4=~address-bit(61)
cmp.ne p8,p0=r0,r23
(p9) cmp.eq.or.andcm p6,p7=IA64_ISR_CODE_LFETCH,r22 // check isr.code field
-(p8) br.cond.spnt page_fault
+(p8) br.cond.spnt ia64_ivt_page_fault

dep r21=-1,r21,IA64_PSR_ED_BIT,1
or r19=r19,r17 // insert PTE control bits into r19
@@ -369,33 +370,6 @@
rfi
END(alt_dtlb_miss)

- //-----------------------------------------------------------------------------------
- // call do_page_fault (predicates are in r31, psr.dt may be off, r16 is faulting address)
-ENTRY(page_fault)
- ssm psr.dt
- ;;
- srlz.i
- ;;
- SAVE_MIN_WITH_COVER
- alloc r15=ar.pfs,0,0,3,0
- mov out0=cr.ifa
- mov out1=cr.isr
- adds r3=8,r2 // set up second base pointer
- ;;
- ssm psr.ic | PSR_DEFAULT_BITS
- ;;
- srlz.i // guarantee that interruption collectin is on
- ;;
-(p15) ssm psr.i // restore psr.i
- movl r14=ia64_leave_kernel
- ;;
- SAVE_REST
- mov rp=r14
- ;;
- adds out2,r12 // out2 = pointer to pt_regs
- br.call.sptk.many b6=ia64_do_page_fault // ignore return address
-END(page_fault)
-
.align 1024
///////////////////////////////////////////////////////////////////////////////////////// // 0x1400 Entry 5 (size 64 bundles) Data nested TLB (6,45)
@@ -407,8 +381,8 @@
* table is missing, a nested TLB miss fault is triggered and control is
* transferred to this point. When this happens, we lookup the pte for the
* faulting address by walking the page table in physical mode and return to the
- * continuation point passed in register r30 (or call page_fault if the address is
- * not mapped).
+ * continuation point passed in register r30 (or call ia64_ivt_page_fault if the
+ * address is not mapped).
*
* Input: r16: faulting address
* r29: saved b0
@@ -452,7 +426,7 @@
;;
(p7) cmp.eq.or.andcm p6,p7=r17,r0 // was L2 entry NULL?
dep r17=r19,r17,3,(PAGE_SHIFT-3) // compute address of L3 page table entry
-(p6) br.cond.spnt page_fault
+(p6) br.cond.spnt ia64_ivt_page_fault
mov b0=r30
br.sptk.many b0 // return to continuation point
END(nested_dtlb_miss)
@@ -775,6 +749,43 @@
DBG_FAULT(14)
FAULT(14)

+ /*
+ * Squatting in this space... There is no particular reason for this code to be
+ * here, other than that there happens to be space here that would go unused
+ * otherwise. If this fault ever gets "unreserved", simply moved the following
+ * code to a more suitable spot...
+ */
+
+ //-----------------------------------------------------------------------------------
+ // call ia64_do_page_fault (predicates are in r31, psr.dt may be off, r16 is faulting
+ // address)
+ //-----------------------------------------------------------------------------------
+ .global ia64_ivt_page_fault
+ENTRY(ia64_ivt_page_fault)
+ ssm psr.dt
+ ;;
+ srlz.i
+ ;;
+ SAVE_MIN_WITH_COVER
+ alloc r15=ar.pfs,0,0,3,0
+ mov out0=cr.ifa
+ mov out1=cr.isr
+ adds r3=8,r2 // set up second base pointer
+ ;;
+ ssm psr.ic | PSR_DEFAULT_BITS
+ ;;
+ srlz.i // guarantee that interruption collectin is on
+ ;;
+(p15) ssm psr.i // restore psr.i
+ movl r14=ia64_leave_kernel
+ ;;
+ SAVE_REST
+ mov rp=r14
+ ;;
+ adds out2,r12 // out2 = pointer to pt_regs
+ br.call.sptk.many b6=ia64_do_page_fault // ignore return address
+END(ia64_ivt_page_fault)
+
.align 1024
///////////////////////////////////////////////////////////////////////////////////////// // 0x3c00 Entry 15 (size 64 bundles) Reserved
@@ -1039,7 +1050,7 @@
;;
mov r31=pr
srlz.d
- br.sptk.many page_fault
+ br.sptk.many ia64_ivt_page_fault
END(page_not_present)

.align 256
@@ -1052,7 +1063,7 @@
mov r31=pr
;;
srlz.d
- br.sptk.many page_fault
+ br.sptk.many ia64_ivt_page_fault
END(key_permission)

.align 256
@@ -1065,7 +1076,7 @@
mov r31=pr
;;
srlz.d
- br.sptk.many page_fault
+ br.sptk.many ia64_ivt_page_fault
END(iaccess_rights)

.align 256
@@ -1078,7 +1089,7 @@
mov r31=pr
;;
srlz.d
- br.sptk.many page_fault
+ br.sptk.many ia64_ivt_page_fault
END(daccess_rights)

.align 256

diff -Nru a/arch/ia64/sn/kernel/Makefile b/arch/ia64/sn/kernel/Makefile
@@ -47,6 +47,7 @@
 obj-y				= probe.o setup.o sv.o bte.o
 obj-y			        += irq.o mca.o idle.o
 obj-y			        += sn2/sn2.o
+obj-y			        += sn2/sn_ivt.o
 
 obj-$(CONFIG_IA64_GENERIC)      += machvec.o
 obj-$(CONFIG_MODULES)           += sn_ksyms.o