LLC-* events not working on sandybridge
Hi,
I've run into a problem with perf on an Intel Sandybridge machine: The LLC-* events never seem to trigger.
For example:
$ perf stat -e LLC-load-misses ls /
[...]
0 LLC-load-misses0.001082639 seconds time elapsed
Non-LLC events work fine:
$ perf stat -e cache-misses ls /
[...]
4,272 cache-misses0.002945606 seconds time elapsed
This is on a Intel i5 machine (i5-2520M), running a fully updated Fedora 16 ('perf --version': 3.3.2-6.fc16.x86_64, 'uname -r':
3.3.2-6.fc16.x86_64).
Any ideas?
David
Hi,
Quoted 21 lines · David Wragg
Hi,
I've run into a problem with perf on an Intel Sandybridge machine: The LLC-* events never seem to trigger.
For example:
$ perf stat -e LLC-load-misses ls / [...] 0 LLC-load-misses0.001082639 seconds time elapsedNon-LLC events work fine:
$ perf stat -e cache-misses ls / [...] 4,272 cache-misses0.002945606 seconds time elapsed
Quoted 7 lines
This is on a Intel i5 machine (i5-2520M), running a fully updated Fedora 16 ('perf --version': 3.3.2-6.fc16.x86_64, 'uname -r':
3.3.2-6.fc16.x86_64).Any ideas?
David
I have a same problem on my i7-3930K machine. I guess it's because of lacking of extra register (MSP_OFFCORE_RSP_X) settings. But I have no idea of how I can set it properly :(.
Thanks,
Namhyung
Quoted 8 lines · Namhyung Kim
Quoted 3 lines · David Wragg
I've run into a problem with perf on an Intel Sandybridge machine: The LLC-* events never seem to trigger.
[...]I have a same problem on my i7-3930K machine. I guess it's because of lacking of extra register (
MSP_OFFCORE_RSP_X) settings. But I have no idea of how I can set it properly :(.
Ok, I've done some further digging around, and it doesn't look like the patch "perf events, x86: Implement Sandybridge last-level cache events" at <https://lkml.org/lkml/2011/5/9/80> ever got merged. It's not clear why.
David
Hi,
Quoted 6 lines · David Wragg
Quoted 5 lines · Namhyung Kim
Quoted 3 lines · David Wragg
I've run into a problem with perf on an Intel Sandybridge machine: The LLC-* events never seem to trigger.
[...]
Quoted 9 lines
Quoted 3 lines
I have a same problem on my i7-3930K machine. I guess it's because of lacking of extra register (
MSP_OFFCORE_RSP_X) settings. But I have no idea of how I can set it properly :(.Ok, I've done some further digging around, and it doesn't look like the patch "perf events, x86: Implement Sandybridge last-level cache events" at <https://lkml.org/lkml/2011/5/9/80> ever got merged. It's not clear why.
It seems that PeterZ and Ingo don't want an unverified patch get merged. But you can still test with it and, hopefully, provide us a verification :).
Thanks,
Namhyung
Quoted 10 lines · Namhyung Kim
Quoted 5 lines · David Wragg
Ok, I've done some further digging around, and it doesn't look like the patch "perf events, x86: Implement Sandybridge last-level cache events" at <https://lkml.org/lkml/2011/5/9/80> ever got merged. It's not clear why.
It seems that PeterZ and Ingo don't want an unverified patch get merged. But you can still test with it and, hopefully, provide us a verification :).
I fixed the patch up for 3.3, and it works for me. I'll ask Lin Ming what happened to it.
David