x86/tsc: fast calibration updates
cover x86/tsc: fast calibration updates
Originally I wrote this series to increase TSC calibration accuracy and speed, but it now it also includes changes that are mandatory for some systems to work correctly. In particular, the Airmont table entires are already being used in products, and some BXT steppings will fail without the check added by patch 10.
LKP tested this patch series in early April on top of 4.6-rc1 and found a failure. That failure has been fixed upstream in 4.6 by commit 886123fb3a86
(x86/tsc: Read all ratio bits from MSR_PLATFORM_INFO)
So I have re-based the series on top of 4.7-rc3 to take advantage of that fix, as well as to handle 3 merge conflicts due to intervening upstream commits.
The series now starts by reverting e2724e9d9692 (x86/tsc: Add missing Cherrytrail frequency to the table) as that is replaced by the more correct and complete "x86 tsc_msr: Add Airmont reference clock values" in this series.
Also, syntax changes were necessary to both
"x86 tsc: enumerate SKL cpu_khz and tsc_khz via CPUID" "x86 tsc: enumerate BXT tsc_khz via CPUID"
in response to cleanups recently applied upstream to tsc.c
[PATCH 01/10] Revert "x86/tsc: Add missing Cherrytrail frequency to [PATCH 02/10] x86 tsc_msr: Identify Intel-specific code [PATCH 03/10] x86 tsc_msr: Remove debugging messages [PATCH 04/10] x86 tsc_msr: Update comments, expand definitions [PATCH 05/10] x86 tsc_msr: Correct Silvermont reference clock values [PATCH 06/10] x86 tsc_msr: Add Airmont reference clock values [PATCH 07/10] x86 tsc_msr: Extend to include Intel Core Architecture [PATCH 08/10] x86 tsc_msr: Remove irqoff around MSR-based TSC [PATCH 09/10] x86 tsc: enumerate SKL cpu_khz and tsc_khz via CPUID [PATCH 10/10] x86 tsc: enumerate BXT tsc_khz via CPUID
PATCH 1/10 Revert "x86/tsc: Add missing Cherrytrail frequency to the table"
From: Len Brown <[email protected]>
This reverts commit e2724e9d969294879936daf7833d4adda26c8efc.
as it is incomplete, and is replaced by a more complete pach later in this series.
--- arch/x86/kernel/tsc_msr.c | 3 --- 1 file changed, 3 deletions(-)
arch/x86/kernel/tsc_msr.c +0 -3
@@ -23,7 +23,6 @@#include <asm/param.h> /* CPU reference clock frequency: in KHz */ -#define FREQ_80 80000#define FREQ_83 83200#define FREQ_100 99840#define FREQ_133 133200
@@ -57,8 +56,6 @@ static struct freq_desc freq_desc_tables[] = { { 6, 0x37, 1, { FREQ_83, FREQ_100, FREQ_133, FREQ_166, 0, 0, 0, 0 } },/* ANN */ { 6, 0x5a, 1, { FREQ_83, FREQ_100, FREQ_133, FREQ_100, 0, 0, 0, 0 } }, -/* AIRMONT */ - { 6, 0x4c, 1, { FREQ_83, FREQ_100, FREQ_133, FREQ_166, FREQ_80, 0, 0, 0 } }, };static int match_cpu (u8 family,u8 model)
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merge bot[tip:x86/timers] Revert "x86/tsc: Add missing Cherrytrail frequency to the table"
Revert "x86/tsc: Add missing Cherrytrail frequency to the table"
Commit-ID: fc5f3ac24720012909c224a63ca3217f4759967d Gitweb: http://git.kernel.org/tip/fc5f3ac24720012909c224a63ca3217f4759967d Author: Len Brown <[email protected]> AuthorDate: Fri, 17 Jun 2016 01:22:43 -0400 Committer: Ingo Molnar <[email protected]> CommitDate: Sun, 10 Jul 2016 17:00:12 +0200
Revert "x86/tsc: Add missing Cherrytrail frequency to the table"
This reverts commit:
e2724e9d9692 ("x86/tsc: Add missing Cherrytrail frequency to the table")
... as it is incomplete, and is replaced by a more complete patch later in this series.
--- arch/x86/kernel/tsc_msr.c | 3 --- 1 file changed, 3 deletions(-)
arch/x86/kernel/tsc_msr.c +0 -3
@@ -23,7 +23,6 @@#include <asm/param.h> /* CPU reference clock frequency: in KHz */ -#define FREQ_80 80000#define FREQ_83 83200#define FREQ_100 99840#define FREQ_133 133200
@@ -57,8 +56,6 @@ static struct freq_desc freq_desc_tables[] = { { 6, 0x37, 1, { FREQ_83, FREQ_100, FREQ_133, FREQ_166, 0, 0, 0, 0 } },/* ANN */ { 6, 0x5a, 1, { FREQ_83, FREQ_100, FREQ_133, FREQ_100, 0, 0, 0, 0 } }, -/* AIRMONT */ - { 6, 0x4c, 1, { FREQ_83, FREQ_100, FREQ_133, FREQ_166, FREQ_80, 0, 0, 0 } }, };static int match_cpu (u8 family,u8 model)
PATCH 2/10 x86 tsc_msr: Identify Intel-specific code
In reply to Len BrownFrom: Len Brown <[email protected]>
try_msr_calibrate_tsc() is currently Intel-specific, and should not execute on any other vendor's parts.
--- arch/x86/kernel/tsc_msr.c | 3 +++ 1 file changed, 3 insertions(+)
arch/x86/kernel/tsc_msr.c +3 -0
@@ -86,6 +86,9 @@ unsigned long try_msr_calibrate_tsc(void)unsigned long res;int cpu_index; +if (boot_cpu_data.x86_vendor !=X86_VENDOR_INTEL ) +return 0 ; + cpu_index =match_cpu (boot_cpu_data.x86, boot_cpu_data.x86_model);if (cpu_index <0 )return 0 ;
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merge bot[tip:x86/timers] x86/tsc_msr: Identify Intel-specific code
x86/tsc_msr: Identify Intel-specific code
Commit-ID: ba8268330dc18d309a39175ea4d2c5d86c2cef09 Gitweb: http://git.kernel.org/tip/ba8268330dc18d309a39175ea4d2c5d86c2cef09 Author: Len Brown <[email protected]> AuthorDate: Fri, 17 Jun 2016 01:22:44 -0400 Committer: Ingo Molnar <[email protected]> CommitDate: Sun, 10 Jul 2016 17:00:12 +0200
x86/tsc_msr: Identify Intel-specific code
try_msr_calibrate_tsc() is currently Intel-specific, and should not execute on any other vendor's parts.
--- arch/x86/kernel/tsc_msr.c | 3 +++ 1 file changed, 3 insertions(+)
arch/x86/kernel/tsc_msr.c +3 -0
@@ -86,6 +86,9 @@ unsigned long try_msr_calibrate_tsc(void)unsigned long res;int cpu_index; +if (boot_cpu_data.x86_vendor !=X86_VENDOR_INTEL ) +return 0 ; + cpu_index =match_cpu (boot_cpu_data.x86, boot_cpu_data.x86_model);if (cpu_index <0 )return 0 ;
PATCH 3/10 x86 tsc_msr: Remove debugging messages
In reply to Len BrownFrom: Len Brown <[email protected]>
Debugging messages are not necessary after all of the possible hardware failures that never occur. Instead, this code can simply return 0.
This code also doesn't need to print in the success case. tsc_init() already prints the TSC frequency,
and apic=debug is available if anybody really is interested in printing the LAPIC frequency.
--- arch/x86/kernel/tsc_msr.c | 19 +++---------------- 1 file changed, 3 insertions(+), 16 deletions(-)
arch/x86/kernel/tsc_msr.c +3 -16
@@ -76,9 +76,10 @@ static int match_cpu(u8 family, u8 model) (freq_desc_tables[cpu_index].freqs[freq_id])/* -* Do MSR calibration only for known/supported CPUs. +* MSR-based CPU/TSC frequency discovery for certain CPUs. * -* Returns the calibration value or 0 if MSR calibration failed. +* Set global "lapic_timer_frequency" to bus_clock_cycles/jiffy +* Return processor base frequency in KHz, or 0 on failure. */unsigned long try_msr_calibrate_tsc (void ) {
@@ -100,31 +101,17 @@ unsigned long try_msr_calibrate_tsc(void)rdmsr (MSR_IA32_PERF_STATUS , lo, hi); ratio = (hi >>8 ) &0x1f ; } -pr_info ("Maximum core-clock to bus-clock ratio: 0x%x\n" , ratio); - -if (!ratio) - goto fail;/* Get FSB FREQ ID */ rdmsr (MSR_FSB_FREQ , lo, hi); freq_id = lo &0x7 ; freq =id_to_freq (cpu_index, freq_id); -pr_info ("Resolved frequency ID: %u, frequency: %u KHz\n" , - freq_id, freq); -if (!freq) - goto fail;/* TSC frequency = maximum resolved freq * maximum resolved bus ratio */ res = freq * ratio; -pr_info ("TSC runs at %lu KHz\n" , res);#ifdef CONFIG_X86_LOCAL_APIC lapic_timer_frequency = (freq *1000 ) /HZ ; -pr_info ("lapic_timer_frequency = %d\n" , lapic_timer_frequency);#endif return res; - -fail: -pr_warn ("Fast TSC calibration using MSR failed\n" ); -return 0 ; }
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merge bot[tip:x86/timers] x86/tsc_msr: Remove debugging messages
x86/tsc_msr: Remove debugging messages
Commit-ID: 14bb4e34860af48ef1ea0f52b11611ce4db987fe Gitweb: http://git.kernel.org/tip/14bb4e34860af48ef1ea0f52b11611ce4db987fe Author: Len Brown <[email protected]> AuthorDate: Fri, 17 Jun 2016 01:22:45 -0400 Committer: Ingo Molnar <[email protected]> CommitDate: Sun, 10 Jul 2016 17:00:13 +0200
x86/tsc_msr: Remove debugging messages
Debugging messages are not necessary after all of the possible hardware failures that never occur. Instead, this code can simply return 0.
This code also doesn't need to print in the success case. tsc_init() already prints the TSC frequency,
and apic=debug is available if anybody really is interested in printing the LAPIC frequency.
--- arch/x86/kernel/tsc_msr.c | 19 +++---------------- 1 file changed, 3 insertions(+), 16 deletions(-)
arch/x86/kernel/tsc_msr.c +3 -16
@@ -76,9 +76,10 @@ static int match_cpu(u8 family, u8 model) (freq_desc_tables[cpu_index].freqs[freq_id])/* -* Do MSR calibration only for known/supported CPUs. +* MSR-based CPU/TSC frequency discovery for certain CPUs. * -* Returns the calibration value or 0 if MSR calibration failed. +* Set global "lapic_timer_frequency" to bus_clock_cycles/jiffy +* Return processor base frequency in KHz, or 0 on failure. */unsigned long try_msr_calibrate_tsc (void ) {
@@ -100,31 +101,17 @@ unsigned long try_msr_calibrate_tsc(void)rdmsr (MSR_IA32_PERF_STATUS , lo, hi); ratio = (hi >>8 ) &0x1f ; } -pr_info ("Maximum core-clock to bus-clock ratio: 0x%x\n" , ratio); - -if (!ratio) - goto fail;/* Get FSB FREQ ID */ rdmsr (MSR_FSB_FREQ , lo, hi); freq_id = lo &0x7 ; freq =id_to_freq (cpu_index, freq_id); -pr_info ("Resolved frequency ID: %u, frequency: %u KHz\n" , - freq_id, freq); -if (!freq) - goto fail;/* TSC frequency = maximum resolved freq * maximum resolved bus ratio */ res = freq * ratio; -pr_info ("TSC runs at %lu KHz\n" , res);#ifdef CONFIG_X86_LOCAL_APIC lapic_timer_frequency = (freq *1000 ) /HZ ; -pr_info ("lapic_timer_frequency = %d\n" , lapic_timer_frequency);#endif return res; - -fail: -pr_warn ("Fast TSC calibration using MSR failed\n" ); -return 0 ; }
PATCH 4/10 x86 tsc_msr: Update comments, expand definitions
In reply to Len BrownFrom: Len Brown <[email protected]>
Syntax only, no functional change.
--- arch/x86/kernel/tsc_msr.c | 36 ++++++++++-------------------------- 1 file changed, 10 insertions(+), 26 deletions(-)
arch/x86/kernel/tsc_msr.c +10 -26
@@ -1,14 +1,5 @@/* -* tsc_msr.c - MSR based TSC calibration on Intel Atom SoC platforms. -* -* TSC in Intel Atom SoC runs at a constant rate which can be figured -* by this formula: -* <maximum core-clock to bus-clock ratio> * <maximum resolved frequency> -* See Intel 64 and IA-32 System Programming Guid section 16.12 and 30.11.5 -* for details. -* Especially some Intel Atom SoCs don't have PIT(i8254) or HPET, so MSR -* based calibration is the only option. -* +* tsc_msr.c - TSC frequency enumeration via MSR * * Copyright (C) 2013 Intel Corporation * Author: Bin Gao <[email protected]>
@@ -22,17 +13,10 @@#include <asm/apic.h> #include <asm/param.h> -/* CPU reference clock frequency: in KHz */ -#define FREQ_83 83200 -#define FREQ_100 99840 -#define FREQ_133 133200 -#define FREQ_166 166400 -#define MAX_NUM_FREQS 8/* -* According to Intel 64 and IA-32 System Programming Guide, -* if MSR_PERF_STAT[31] is set, the maximum resolved bus ratio can be +* If MSR_PERF_STAT[31] is set, the maximum resolved bus ratio can be * read in MSR_PLATFORM_ID[12:8], otherwise in MSR_PERF_STAT[44:40]. * Unfortunately some Intel Atom SoCs aren't quite compliant to this, * so we need manually differentiate SoC families. This is what the
@@ -47,15 +31,15 @@ struct freq_desc {static struct freq_desc freq_desc_tables[] = {/* PNW */ - {6 ,0x27 ,0 , {0 ,0 ,0 ,0 ,0 ,FREQ_100 ,0 ,FREQ_83 } }, + {6 ,0x27 ,0 , {0 ,0 ,0 ,0 ,0 ,99840 ,0 ,83200 } },/* CLV+ */ - {6 ,0x35 ,0 , {0 ,FREQ_133 ,0 ,0 ,0 ,FREQ_100 ,0 ,FREQ_83 } }, -/* TNG */ - {6 ,0x4a ,1 , {0 ,FREQ_100 ,FREQ_133 ,0 ,0 ,0 ,0 ,0 } }, -/* VLV2 */ - {6 ,0x37 ,1 , {FREQ_83 ,FREQ_100 ,FREQ_133 ,FREQ_166 ,0 ,0 ,0 ,0 } }, -/* ANN */ - {6 ,0x5a ,1 , {FREQ_83 ,FREQ_100 ,FREQ_133 ,FREQ_100 ,0 ,0 ,0 ,0 } }, + {6 ,0x35 ,0 , {0 ,133200 ,0 ,0 ,0 ,99840 ,0 ,83200 } }, +/* TNG - Intel Atom processor Z3400 series */ + {6 ,0x4a ,1 , {0 ,99840 ,133200 ,0 ,0 ,0 ,0 ,0 } }, +/* VLV2 - Intel Atom processor E3000, Z3600, Z3700 series */ + {6 ,0x37 ,1 , {83200 ,99840 ,133200 ,166400 ,0 ,0 ,0 ,0 } }, +/* ANN - Intel Atom processor Z3500 series */ + {6 ,0x5a ,1 , {83200 ,99840 ,133200 ,99840 ,0 ,0 ,0 ,0 } }, };static int match_cpu (u8 family,u8 model)
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merge bot[tip:x86/timers] x86/tsc_msr: Update comments, expand definitions
x86/tsc_msr: Update comments, expand definitions
Commit-ID: 9e0cae9f6227f946fb0076b6a68c88156137f618 Gitweb: http://git.kernel.org/tip/9e0cae9f6227f946fb0076b6a68c88156137f618 Author: Len Brown <[email protected]> AuthorDate: Fri, 17 Jun 2016 01:22:46 -0400 Committer: Ingo Molnar <[email protected]> CommitDate: Sun, 10 Jul 2016 17:00:13 +0200
x86/tsc_msr: Update comments, expand definitions
Syntax only, no functional change.
--- arch/x86/kernel/tsc_msr.c | 36 ++++++++++-------------------------- 1 file changed, 10 insertions(+), 26 deletions(-)
arch/x86/kernel/tsc_msr.c +10 -26
@@ -1,14 +1,5 @@/* -* tsc_msr.c - MSR based TSC calibration on Intel Atom SoC platforms. -* -* TSC in Intel Atom SoC runs at a constant rate which can be figured -* by this formula: -* <maximum core-clock to bus-clock ratio> * <maximum resolved frequency> -* See Intel 64 and IA-32 System Programming Guid section 16.12 and 30.11.5 -* for details. -* Especially some Intel Atom SoCs don't have PIT(i8254) or HPET, so MSR -* based calibration is the only option. -* +* tsc_msr.c - TSC frequency enumeration via MSR * * Copyright (C) 2013 Intel Corporation * Author: Bin Gao <[email protected]>
@@ -22,17 +13,10 @@#include <asm/apic.h> #include <asm/param.h> -/* CPU reference clock frequency: in KHz */ -#define FREQ_83 83200 -#define FREQ_100 99840 -#define FREQ_133 133200 -#define FREQ_166 166400 -#define MAX_NUM_FREQS 8/* -* According to Intel 64 and IA-32 System Programming Guide, -* if MSR_PERF_STAT[31] is set, the maximum resolved bus ratio can be +* If MSR_PERF_STAT[31] is set, the maximum resolved bus ratio can be * read in MSR_PLATFORM_ID[12:8], otherwise in MSR_PERF_STAT[44:40]. * Unfortunately some Intel Atom SoCs aren't quite compliant to this, * so we need manually differentiate SoC families. This is what the
@@ -47,15 +31,15 @@ struct freq_desc {static struct freq_desc freq_desc_tables[] = {/* PNW */ - {6 ,0x27 ,0 , {0 ,0 ,0 ,0 ,0 ,FREQ_100 ,0 ,FREQ_83 } }, + {6 ,0x27 ,0 , {0 ,0 ,0 ,0 ,0 ,99840 ,0 ,83200 } },/* CLV+ */ - {6 ,0x35 ,0 , {0 ,FREQ_133 ,0 ,0 ,0 ,FREQ_100 ,0 ,FREQ_83 } }, -/* TNG */ - {6 ,0x4a ,1 , {0 ,FREQ_100 ,FREQ_133 ,0 ,0 ,0 ,0 ,0 } }, -/* VLV2 */ - {6 ,0x37 ,1 , {FREQ_83 ,FREQ_100 ,FREQ_133 ,FREQ_166 ,0 ,0 ,0 ,0 } }, -/* ANN */ - {6 ,0x5a ,1 , {FREQ_83 ,FREQ_100 ,FREQ_133 ,FREQ_100 ,0 ,0 ,0 ,0 } }, + {6 ,0x35 ,0 , {0 ,133200 ,0 ,0 ,0 ,99840 ,0 ,83200 } }, +/* TNG - Intel Atom processor Z3400 series */ + {6 ,0x4a ,1 , {0 ,99840 ,133200 ,0 ,0 ,0 ,0 ,0 } }, +/* VLV2 - Intel Atom processor E3000, Z3600, Z3700 series */ + {6 ,0x37 ,1 , {83200 ,99840 ,133200 ,166400 ,0 ,0 ,0 ,0 } }, +/* ANN - Intel Atom processor Z3500 series */ + {6 ,0x5a ,1 , {83200 ,99840 ,133200 ,99840 ,0 ,0 ,0 ,0 } }, };static int match_cpu (u8 family,u8 model)
PATCH 5/10 x86 tsc_msr: Correct Silvermont reference clock values
In reply to Len BrownFrom: Len Brown <[email protected]>
Atom processors use a 19.2 MHz crystal oscillator.
Early processors generate 100 MHz via 19.2 MHz * 26 / 5 = 99.84 MHz.
Later preocessor generate 100 MHz via 19.2 MHz * 125 / 24 = 100 MHz.
Update the Silvermont-based tables accordingly,
matching the Software Developers Manual.
Also, correct a 166 MHz entry that should have been 116 MHz, and add a missing 80 MHz entry.
--- arch/x86/kernel/tsc_msr.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)
arch/x86/kernel/tsc_msr.c +3 -3
@@ -35,11 +35,11 @@ static struct freq_desc freq_desc_tables[] = {/* CLV+ */ { 6, 0x35, 0, { 0, 133200, 0, 0, 0, 99840, 0, 83200 } },/* TNG - Intel Atom processor Z3400 series */ - { 6, 0x4a, 1, { 0, 99840, 133200, 0, 0, 0, 0, 0 } }, + { 6, 0x4a, 1, { 0, 100000, 133300, 0, 0, 0, 0, 0 } },/* VLV2 - Intel Atom processor E3000, Z3600, Z3700 series */ - { 6, 0x37, 1, { 83200, 99840, 133200, 166400, 0, 0, 0, 0 } }, + { 6, 0x37, 1, { 83300, 100000, 133300, 116700, 80000, 0, 0, 0 } },/* ANN - Intel Atom processor Z3500 series */ - { 6, 0x5a, 1, { 83200, 99840, 133200, 99840, 0, 0, 0, 0 } }, + { 6, 0x5a, 1, { 83300, 100000, 133300, 100000, 0, 0, 0, 0 } }, };static int match_cpu (u8 family,u8 model)
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merge bot[tip:x86/timers] x86/tsc_msr: Correct Silvermont reference clock values
x86/tsc_msr: Correct Silvermont reference clock values
Commit-ID: 05680e7fa8a4e700e031a5e72cd8c18265f0031a Gitweb: http://git.kernel.org/tip/05680e7fa8a4e700e031a5e72cd8c18265f0031a Author: Len Brown <[email protected]> AuthorDate: Fri, 17 Jun 2016 01:22:47 -0400 Committer: Ingo Molnar <[email protected]> CommitDate: Sun, 10 Jul 2016 17:00:13 +0200
x86/tsc_msr: Correct Silvermont reference clock values
Atom processors use a 19.2 MHz crystal oscillator.
Early processors generate 100 MHz via 19.2 MHz * 26 / 5 = 99.84 MHz.
Later preocessor generate 100 MHz via 19.2 MHz * 125 / 24 = 100 MHz.
Update the Silvermont-based tables accordingly,
matching the Software Developers Manual.
Also, correct a 166 MHz entry that should have been 116 MHz, and add a missing 80 MHz entry.
--- arch/x86/kernel/tsc_msr.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)
arch/x86/kernel/tsc_msr.c +3 -3
@@ -35,11 +35,11 @@ static struct freq_desc freq_desc_tables[] = {/* CLV+ */ { 6, 0x35, 0, { 0, 133200, 0, 0, 0, 99840, 0, 83200 } },/* TNG - Intel Atom processor Z3400 series */ - { 6, 0x4a, 1, { 0, 99840, 133200, 0, 0, 0, 0, 0 } }, + { 6, 0x4a, 1, { 0, 100000, 133300, 0, 0, 0, 0, 0 } },/* VLV2 - Intel Atom processor E3000, Z3600, Z3700 series */ - { 6, 0x37, 1, { 83200, 99840, 133200, 166400, 0, 0, 0, 0 } }, + { 6, 0x37, 1, { 83300, 100000, 133300, 116700, 80000, 0, 0, 0 } },/* ANN - Intel Atom processor Z3500 series */ - { 6, 0x5a, 1, { 83200, 99840, 133200, 99840, 0, 0, 0, 0 } }, + { 6, 0x5a, 1, { 83300, 100000, 133300, 100000, 0, 0, 0, 0 } }, };static int match_cpu (u8 family,u8 model)
PATCH 6/10 x86 tsc_msr: Add Airmont reference clock values
In reply to Len BrownFrom: Len Brown <[email protected]>
per the Intel 64 and IA-32 Architecture Software Developer's Manual...
Add the reference clock for Intel Atom Processors
Based on the Airmont Microarchitecture.
--- arch/x86/kernel/tsc_msr.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-)
arch/x86/kernel/tsc_msr.c +4 -1
@@ -13,7 +13,7 @@#include <asm/apic.h> #include <asm/param.h> -#define MAX_NUM_FREQS 8 +#define MAX_NUM_FREQS 9/* * If MSR_PERF_STAT[31] is set, the maximum resolved bus ratio can be
@@ -40,6 +40,9 @@ static struct freq_desc freq_desc_tables[] = { { 6, 0x37, 1, { 83300, 100000, 133300, 116700, 80000, 0, 0, 0 } },/* ANN - Intel Atom processor Z3500 series */ { 6, 0x5a, 1, { 83300, 100000, 133300, 100000, 0, 0, 0, 0 } }, +/* AMT - Intel Atom processor X7-Z8000 and X5-Z8000 series */ + { 6, 0x4c, 1, { 83300, 100000, 133300, 116700, + 80000, 93300, 90000, 88900, 87500 } }, };static int match_cpu (u8 family,u8 model)
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merge bot[tip:x86/timers] x86/tsc_msr: Add Airmont reference clock values
x86/tsc_msr: Add Airmont reference clock values
Commit-ID: 6fcb41cdaee5056c96de88ee095bddd27a7697de Gitweb: http://git.kernel.org/tip/6fcb41cdaee5056c96de88ee095bddd27a7697de Author: Len Brown <[email protected]> AuthorDate: Fri, 17 Jun 2016 01:22:48 -0400 Committer: Ingo Molnar <[email protected]> CommitDate: Sun, 10 Jul 2016 17:00:13 +0200
x86/tsc_msr: Add Airmont reference clock values
per the Intel 64 and IA-32 Architecture Software Developer's Manual...
Add the reference clock for Intel Atom Processors
Based on the Airmont Microarchitecture.
--- arch/x86/kernel/tsc_msr.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-)
arch/x86/kernel/tsc_msr.c +4 -1
@@ -13,7 +13,7 @@#include <asm/apic.h> #include <asm/param.h> -#define MAX_NUM_FREQS 8 +#define MAX_NUM_FREQS 9/* * If MSR_PERF_STAT[31] is set, the maximum resolved bus ratio can be
@@ -40,6 +40,9 @@ static struct freq_desc freq_desc_tables[] = { { 6, 0x37, 1, { 83300, 100000, 133300, 116700, 80000, 0, 0, 0 } },/* ANN - Intel Atom processor Z3500 series */ { 6, 0x5a, 1, { 83300, 100000, 133300, 100000, 0, 0, 0, 0 } }, +/* AMT - Intel Atom processor X7-Z8000 and X5-Z8000 series */ + { 6, 0x4c, 1, { 83300, 100000, 133300, 116700, + 80000, 93300, 90000, 88900, 87500 } }, };static int match_cpu (u8 family,u8 model)
PATCH 7/10 x86 tsc_msr: Extend to include Intel Core Architecture
In reply to Len BrownFrom: Len Brown <[email protected]>
tsc_msr is used to quickly and reliably
enumerate the CPU/TSC frequencies at boot time
For the Intel Atom Architecture.
Extend tsc_msr to include recent Intel Core Architecture.
As this code discovers BCLK, it also sets lapic_timer_frequency, which allows LAPIC timer calibration to be skipped, though it is already skipped on systems with a TSC deadline timer.
--- arch/x86/kernel/tsc_msr.c | 49 +++++++++++++++++++++++++++++++++++++++-------- 1 file changed, 41 insertions(+), 8 deletions(-)
arch/x86/kernel/tsc_msr.c +41 -8
@@ -77,23 +77,56 @@ unsigned long try_msr_calibrate_tsc(void)if (boot_cpu_data.x86_vendor !=X86_VENDOR_INTEL )return 0 ; +/* +* 100 MHz BCLK Core Architecture -- before SKL. +* De-rate 100Mhz by about 0.25% to account +* for the average effect of spread-spectrum clocking. +*/ +switch (boot_cpu_data.x86_model) { + +case 0x2A :/* SNB */ +case 0x3A :/* IVB */ + freq =99773 ; + goto get_ratio; +case 0x2D :/* SNB Xeon */ +case 0x3E :/* IVB Xeon */ + freq =99760 ; + goto get_ratio; +case 0x3C :/* HSW */ +case 0x3F :/* HSW */ +case 0x45 :/* HSW */ +case 0x46 :/* HSW */ +case 0x3D :/* BDW */ +case 0x47 :/* BDW */ +case 0x4F :/* BDX */ +case 0x56 :/* BDX-DE */ + freq =99769 ; + goto get_ratio; + } + +/* +* Atom Architecture +*/ cpu_index =match_cpu (boot_cpu_data.x86, boot_cpu_data.x86_model);if (cpu_index <0 )return 0 ; -if (freq_desc_tables[cpu_index].msr_plat) { -rdmsr (MSR_PLATFORM_INFO , lo, hi); - ratio = (lo >>8 ) &0xff ; - }else { -rdmsr (MSR_IA32_PERF_STATUS , lo, hi); - ratio = (hi >>8 ) &0x1f ; - } -/* Get FSB FREQ ID */ rdmsr (MSR_FSB_FREQ , lo, hi); freq_id = lo &0x7 ; freq =id_to_freq (cpu_index, freq_id); +if (!freq_desc_tables[cpu_index].msr_plat) { +rdmsr (MSR_IA32_PERF_STATUS , lo, hi); + ratio = (hi >>8 ) &0x1f ; + goto done; + } + +get_ratio: +rdmsr (MSR_PLATFORM_INFO , lo, hi); + ratio = (lo >>8 ) &0xff ; + +done:/* TSC frequency = maximum resolved freq * maximum resolved bus ratio */ res = freq * ratio;
Signature · 1 line
2.9.0
tip-bot for Len Brown
merge bot[tip:x86/timers] x86/tsc_msr: Extend to include Intel Core Architecture
x86/tsc_msr: Extend to include Intel Core Architecture
Commit-ID: fc273eeef314cdaf0ac992b400d126f8184a4d1c Gitweb: http://git.kernel.org/tip/fc273eeef314cdaf0ac992b400d126f8184a4d1c Author: Len Brown <[email protected]> AuthorDate: Fri, 17 Jun 2016 01:22:49 -0400 Committer: Ingo Molnar <[email protected]> CommitDate: Sun, 10 Jul 2016 17:00:13 +0200
x86/tsc_msr: Extend to include Intel Core Architecture
tsc_msr is used to quickly and reliably
enumerate the CPU/TSC frequencies at boot time
For the Intel Atom Architecture.
Extend tsc_msr to include recent Intel Core Architecture.
As this code discovers BCLK, it also sets lapic_timer_frequency, which allows LAPIC timer calibration to be skipped, though it is already skipped on systems with a TSC deadline timer.
--- arch/x86/kernel/tsc_msr.c | 49 +++++++++++++++++++++++++++++++++++++++-------- 1 file changed, 41 insertions(+), 8 deletions(-)
arch/x86/kernel/tsc_msr.c +41 -8
@@ -77,23 +77,56 @@ unsigned long try_msr_calibrate_tsc(void)if (boot_cpu_data.x86_vendor !=X86_VENDOR_INTEL )return 0 ; +/* +* 100 MHz BCLK Core Architecture -- before SKL. +* De-rate 100Mhz by about 0.25% to account +* for the average effect of spread-spectrum clocking. +*/ +switch (boot_cpu_data.x86_model) { + +case 0x2A :/* SNB */ +case 0x3A :/* IVB */ + freq =99773 ; + goto get_ratio; +case 0x2D :/* SNB Xeon */ +case 0x3E :/* IVB Xeon */ + freq =99760 ; + goto get_ratio; +case 0x3C :/* HSW */ +case 0x3F :/* HSW */ +case 0x45 :/* HSW */ +case 0x46 :/* HSW */ +case 0x3D :/* BDW */ +case 0x47 :/* BDW */ +case 0x4F :/* BDX */ +case 0x56 :/* BDX-DE */ + freq =99769 ; + goto get_ratio; + } + +/* +* Atom Architecture +*/ cpu_index =match_cpu (boot_cpu_data.x86, boot_cpu_data.x86_model);if (cpu_index <0 )return 0 ; -if (freq_desc_tables[cpu_index].msr_plat) { -rdmsr (MSR_PLATFORM_INFO , lo, hi); - ratio = (lo >>8 ) &0xff ; - }else { -rdmsr (MSR_IA32_PERF_STATUS , lo, hi); - ratio = (hi >>8 ) &0x1f ; - } -/* Get FSB FREQ ID */ rdmsr (MSR_FSB_FREQ , lo, hi); freq_id = lo &0x7 ; freq =id_to_freq (cpu_index, freq_id); +if (!freq_desc_tables[cpu_index].msr_plat) { +rdmsr (MSR_IA32_PERF_STATUS , lo, hi); + ratio = (hi >>8 ) &0x1f ; + goto done; + } + +get_ratio: +rdmsr (MSR_PLATFORM_INFO , lo, hi); + ratio = (lo >>8 ) &0xff ; + +done:/* TSC frequency = maximum resolved freq * maximum resolved bus ratio */ res = freq * ratio;
PATCH 8/10 x86 tsc_msr: Remove irqoff around MSR-based TSC enumeration
In reply to Len BrownFrom: Len Brown <[email protected]>
Remove the irqoff/irqon around MSR-based TSC enumeration, as it is not necessary.
Also rename: try_msr_calibrate_tsc() to cpu_khz_from_msr(), as that better describes what the routine does.
--- arch/x86/include/asm/tsc.h | 3 +-- arch/x86/kernel/tsc.c | 5 +---- arch/x86/kernel/tsc_msr.c | 2 +- 3 files changed, 3 insertions(+), 7 deletions(-)
arch/x86/include/asm/tsc.h +1 -2
@@ -52,7 +52,6 @@ extern int notsc_setup(char *);extern void tsc_save_sched_clock_state (void );extern void tsc_restore_sched_clock_state (void ); -/* MSR based TSC calibration for Intel Atom SoC platforms */ -unsigned long try_msr_calibrate_tsc (void ); +unsigned long cpu_khz_from_msr (void );#endif /* _ASM_X86_TSC_H */
arch/x86/kernel/tsc.c +1 -4
@@ -674,10 +674,7 @@ unsigned long native_calibrate_tsc(void)unsigned long flags, latch, ms, fast_calibrate;int hpet =is_hpet_enabled (), i, loopmin; -/* Calibrate TSC using MSR for Intel Atom SoCs */ -local_irq_save (flags); - fast_calibrate =try_msr_calibrate_tsc (); -local_irq_restore (flags); + fast_calibrate =cpu_khz_from_msr ();if (fast_calibrate)return fast_calibrate;
arch/x86/kernel/tsc_msr.c +1 -1
@@ -68,7 +68,7 @@ static int match_cpu(u8 family, u8 model)* Set global "lapic_timer_frequency" to bus_clock_cycles/jiffy * Return processor base frequency in KHz, or 0 on failure. */ -unsigned long try_msr_calibrate_tsc (void ) +unsigned long cpu_khz_from_msr (void ) {u32 lo, hi, ratio, freq_id, freq;unsigned long res;
Signature · 1 line
2.9.0
tip-bot for Len Brown
merge bot[tip:x86/timers] x86/tsc_msr: Remove irqoff around MSR-based TSC enumeration
x86/tsc_msr: Remove irqoff around MSR-based TSC enumeration
Commit-ID: 5c3a67bbfa5cf936c71c7af4e2a3661813819684 Gitweb: http://git.kernel.org/tip/5c3a67bbfa5cf936c71c7af4e2a3661813819684 Author: Len Brown <[email protected]> AuthorDate: Fri, 17 Jun 2016 01:22:50 -0400 Committer: Ingo Molnar <[email protected]> CommitDate: Sun, 10 Jul 2016 17:00:14 +0200
x86/tsc_msr: Remove irqoff around MSR-based TSC enumeration
Remove the irqoff/irqon around MSR-based TSC enumeration, as it is not necessary.
Also rename: try_msr_calibrate_tsc() to cpu_khz_from_msr(), as that better describes what the routine does.
--- arch/x86/include/asm/tsc.h | 3 +-- arch/x86/kernel/tsc.c | 5 +---- arch/x86/kernel/tsc_msr.c | 2 +- 3 files changed, 3 insertions(+), 7 deletions(-)
arch/x86/include/asm/tsc.h +1 -2
@@ -52,7 +52,6 @@ extern int notsc_setup(char *);extern void tsc_save_sched_clock_state (void );extern void tsc_restore_sched_clock_state (void ); -/* MSR based TSC calibration for Intel Atom SoC platforms */ -unsigned long try_msr_calibrate_tsc (void ); +unsigned long cpu_khz_from_msr (void );#endif /* _ASM_X86_TSC_H */
arch/x86/kernel/tsc.c +1 -4
@@ -674,10 +674,7 @@ unsigned long native_calibrate_tsc(void)unsigned long flags, latch, ms, fast_calibrate;int hpet =is_hpet_enabled (), i, loopmin; -/* Calibrate TSC using MSR for Intel Atom SoCs */ -local_irq_save (flags); - fast_calibrate =try_msr_calibrate_tsc (); -local_irq_restore (flags); + fast_calibrate =cpu_khz_from_msr ();if (fast_calibrate)return fast_calibrate;
arch/x86/kernel/tsc_msr.c +1 -1
@@ -68,7 +68,7 @@ static int match_cpu(u8 family, u8 model)* Set global "lapic_timer_frequency" to bus_clock_cycles/jiffy * Return processor base frequency in KHz, or 0 on failure. */ -unsigned long try_msr_calibrate_tsc (void ) +unsigned long cpu_khz_from_msr (void ) {u32 lo, hi, ratio, freq_id, freq;unsigned long res;
tip-bot for Len Brown
merge bot[tip:x86/timers] x86/tsc_msr: Remove irqoff around MSR-based TSC enumeration
In reply to Len Brownx86/tsc_msr: Remove irqoff around MSR-based TSC enumeration
Commit-ID: 02c0cd2dcf7fdc47d054b855b148ea8b82dbb7eb Gitweb: http://git.kernel.org/tip/02c0cd2dcf7fdc47d054b855b148ea8b82dbb7eb Author: Len Brown <[email protected]> AuthorDate: Fri, 17 Jun 2016 01:22:50 -0400 Committer: Ingo Molnar <[email protected]> CommitDate: Mon, 11 Jul 2016 21:30:12 +0200
x86/tsc_msr: Remove irqoff around MSR-based TSC enumeration
Remove the irqoff/irqon around MSR-based TSC enumeration, as it is not necessary.
Also rename: try_msr_calibrate_tsc() to cpu_khz_from_msr(), as that better describes what the routine does.
--- arch/x86/include/asm/tsc.h | 3 +-- arch/x86/kernel/tsc.c | 5 +---- arch/x86/kernel/tsc_msr.c | 2 +- 3 files changed, 3 insertions(+), 7 deletions(-)
arch/x86/include/asm/tsc.h +1 -2
@@ -52,7 +52,6 @@ extern int notsc_setup(char *);extern void tsc_save_sched_clock_state (void );extern void tsc_restore_sched_clock_state (void ); -/* MSR based TSC calibration for Intel Atom SoC platforms */ -unsigned long try_msr_calibrate_tsc (void ); +unsigned long cpu_khz_from_msr (void );#endif /* _ASM_X86_TSC_H */
arch/x86/kernel/tsc.c +1 -4
@@ -674,10 +674,7 @@ unsigned long native_calibrate_tsc(void)unsigned long flags, latch, ms, fast_calibrate;int hpet =is_hpet_enabled (), i, loopmin; -/* Calibrate TSC using MSR for Intel Atom SoCs */ -local_irq_save (flags); - fast_calibrate =try_msr_calibrate_tsc (); -local_irq_restore (flags); + fast_calibrate =cpu_khz_from_msr ();if (fast_calibrate)return fast_calibrate;
arch/x86/kernel/tsc_msr.c +1 -1
@@ -68,7 +68,7 @@ static int match_cpu(u8 family, u8 model)* Set global "lapic_timer_frequency" to bus_clock_cycles/jiffy * Return processor base frequency in KHz, or 0 on failure. */ -unsigned long try_msr_calibrate_tsc (void ) +unsigned long cpu_khz_from_msr (void ) {u32 lo, hi, ratio, freq_id, freq;unsigned long res;
PATCH 9/10 x86 tsc: enumerate SKL cpu_khz and tsc_khz via CPUID
In reply to Len BrownFrom: Len Brown <[email protected]>
Skylake CPU base-frequency and TSC frequency may differ by up to 2%.
Enumerate CPU and TSC frequencies separately, allowing cpu_khz and tsc_khz to differ.
The existing CPU frequency calibration mechanism is unchanged. However, CPUID extensions are preferred, when available.
CPUID.0x16 is preferred over MSR and timer calibration for CPU frequency discovery.
CPUID.0x15 takes precedence over CPU-frequency
for TSC frequency discovery.
--- arch/x86/include/asm/tsc.h | 1 + arch/x86/include/asm/x86_init.h | 4 ++- arch/x86/kernel/tsc.c | 75 +++++++++++++++++++++++++++++++++++++---- arch/x86/kernel/x86_init.c | 1 + 4 files changed, 73 insertions(+), 8 deletions(-)
arch/x86/include/asm/tsc.h +1 -0
@@ -36,6 +36,7 @@ extern void mark_tsc_unstable(char *reason);extern int unsynchronized_tsc (void );extern int check_tsc_unstable (void );extern int check_tsc_disabled (void ); +extern unsigned long native_calibrate_cpu (void );extern unsigned long native_calibrate_tsc (void );extern unsigned long long native_sched_clock_from_tsc (u64 tsc);
arch/x86/include/asm/x86_init.h +3 -1
@@ -181,7 +181,8 @@ struct x86_legacy_features {/** * struct x86_platform_ops - platform specific runtime functions -* @calibrate_tsc: calibrate TSC +* @calibrate_cpu: calibrate CPU +* @calibrate_tsc: calibrate TSC, if different from CPU * @get_wallclock: get time from HW clock like RTC etc. * @set_wallclock: set time back to HW clock * @is_untracked_pat_range exclude from PAT logic
@@ -200,6 +201,7 @@ struct x86_legacy_features {* semantics. */ struct x86_platform_ops { +unsigned long (*calibrate_cpu)(void );unsigned long (*calibrate_tsc)(void );void (*get_wallclock)(struct timespec *ts);int (*set_wallclock)(const struct timespec *ts);
arch/x86/kernel/tsc.c +68 -7
127 lines not on this page · raw message
arch/x86/kernel/x86_init.c +1 -0
@@ -92,6 +92,7 @@ static void default_nmi_init(void) { };static int default_i8042_detect (void ) {return 1 ; };struct x86_platform_ops x86_platform = { + .calibrate_cpu = native_calibrate_cpu, .calibrate_tsc = native_calibrate_tsc, .get_wallclock = mach_get_cmos_time, .set_wallclock = mach_set_rtc_mmss,
Signature · 1 line
2.9.0
tip-bot for Len Brown
merge bot[tip:x86/timers] x86/tsc: Enumerate SKL cpu_khz and tsc_khz via CPUID
x86/tsc: Enumerate SKL cpu_khz and tsc_khz via CPUID
Commit-ID: 1bf8915ae5156dff439d2c65314bd8fdde1b83bf Gitweb: http://git.kernel.org/tip/1bf8915ae5156dff439d2c65314bd8fdde1b83bf Author: Len Brown <[email protected]> AuthorDate: Fri, 17 Jun 2016 01:22:51 -0400 Committer: Ingo Molnar <[email protected]> CommitDate: Sun, 10 Jul 2016 17:00:14 +0200
x86/tsc: Enumerate SKL cpu_khz and tsc_khz via CPUID
Skylake CPU base-frequency and TSC frequency may differ by up to 2%.
Enumerate CPU and TSC frequencies separately, allowing cpu_khz and tsc_khz to differ.
The existing CPU frequency calibration mechanism is unchanged. However, CPUID extensions are preferred, when available.
CPUID.0x16 is preferred over MSR and timer calibration for CPU frequency discovery.
CPUID.0x15 takes precedence over CPU-frequency for TSC frequency discovery.
--- arch/x86/include/asm/tsc.h | 1 + arch/x86/include/asm/x86_init.h | 4 ++- arch/x86/kernel/tsc.c | 75 +++++++++++++++++++++++++++++++++++++---- arch/x86/kernel/x86_init.c | 1 + 4 files changed, 73 insertions(+), 8 deletions(-)
arch/x86/include/asm/tsc.h +1 -0
@@ -36,6 +36,7 @@ extern void mark_tsc_unstable(char *reason);extern int unsynchronized_tsc (void );extern int check_tsc_unstable (void );extern int check_tsc_disabled (void ); +extern unsigned long native_calibrate_cpu (void );extern unsigned long native_calibrate_tsc (void );extern unsigned long long native_sched_clock_from_tsc (u64 tsc);
arch/x86/include/asm/x86_init.h +3 -1
@@ -181,7 +181,8 @@ struct x86_legacy_features {/** * struct x86_platform_ops - platform specific runtime functions -* @calibrate_tsc: calibrate TSC +* @calibrate_cpu: calibrate CPU +* @calibrate_tsc: calibrate TSC, if different from CPU * @get_wallclock: get time from HW clock like RTC etc. * @set_wallclock: set time back to HW clock * @is_untracked_pat_range exclude from PAT logic
@@ -200,6 +201,7 @@ struct x86_legacy_features {* semantics. */ struct x86_platform_ops { +unsigned long (*calibrate_cpu)(void );unsigned long (*calibrate_tsc)(void );void (*get_wallclock)(struct timespec *ts);int (*set_wallclock)(const struct timespec *ts);
arch/x86/kernel/tsc.c +68 -7
127 lines not on this page · raw message
arch/x86/kernel/x86_init.c +1 -0
@@ -92,6 +92,7 @@ static void default_nmi_init(void) { };static int default_i8042_detect (void ) {return 1 ; };struct x86_platform_ops x86_platform = { + .calibrate_cpu = native_calibrate_cpu, .calibrate_tsc = native_calibrate_tsc, .get_wallclock = mach_get_cmos_time, .set_wallclock = mach_set_rtc_mmss,
tip-bot for Len Brown
merge bot[tip:x86/timers] x86/tsc: Enumerate SKL cpu_khz and tsc_khz via CPUID
In reply to Len Brownx86/tsc: Enumerate SKL cpu_khz and tsc_khz via CPUID
Commit-ID: aa297292d708e89773b3b2cdcaf33f01bfa095d8 Gitweb: http://git.kernel.org/tip/aa297292d708e89773b3b2cdcaf33f01bfa095d8 Author: Len Brown <[email protected]> AuthorDate: Fri, 17 Jun 2016 01:22:51 -0400 Committer: Ingo Molnar <[email protected]> CommitDate: Mon, 11 Jul 2016 21:30:13 +0200
x86/tsc: Enumerate SKL cpu_khz and tsc_khz via CPUID
Skylake CPU base-frequency and TSC frequency may differ by up to 2%.
Enumerate CPU and TSC frequencies separately, allowing cpu_khz and tsc_khz to differ.
The existing CPU frequency calibration mechanism is unchanged. However, CPUID extensions are preferred, when available.
CPUID.0x16 is preferred over MSR and timer calibration for CPU frequency discovery.
CPUID.0x15 takes precedence over CPU-frequency for TSC frequency discovery.
--- arch/x86/include/asm/tsc.h | 1 + arch/x86/include/asm/x86_init.h | 4 ++- arch/x86/kernel/tsc.c | 75 +++++++++++++++++++++++++++++++++++++---- arch/x86/kernel/x86_init.c | 1 + 4 files changed, 73 insertions(+), 8 deletions(-)
arch/x86/include/asm/tsc.h +1 -0
@@ -36,6 +36,7 @@ extern void mark_tsc_unstable(char *reason);extern int unsynchronized_tsc (void );extern int check_tsc_unstable (void );extern int check_tsc_disabled (void ); +extern unsigned long native_calibrate_cpu (void );extern unsigned long native_calibrate_tsc (void );extern unsigned long long native_sched_clock_from_tsc (u64 tsc);
arch/x86/include/asm/x86_init.h +3 -1
@@ -181,7 +181,8 @@ struct x86_legacy_features {/** * struct x86_platform_ops - platform specific runtime functions -* @calibrate_tsc: calibrate TSC +* @calibrate_cpu: calibrate CPU +* @calibrate_tsc: calibrate TSC, if different from CPU * @get_wallclock: get time from HW clock like RTC etc. * @set_wallclock: set time back to HW clock * @is_untracked_pat_range exclude from PAT logic
@@ -200,6 +201,7 @@ struct x86_legacy_features {* semantics. */ struct x86_platform_ops { +unsigned long (*calibrate_cpu)(void );unsigned long (*calibrate_tsc)(void );void (*get_wallclock)(struct timespec *ts);int (*set_wallclock)(const struct timespec *ts);
arch/x86/kernel/tsc.c +68 -7
127 lines not on this page · raw message
arch/x86/kernel/x86_init.c +1 -0
@@ -92,6 +92,7 @@ static void default_nmi_init(void) { };static int default_i8042_detect (void ) {return 1 ; };struct x86_platform_ops x86_platform = { + .calibrate_cpu = native_calibrate_cpu, .calibrate_tsc = native_calibrate_tsc, .get_wallclock = mach_get_cmos_time, .set_wallclock = mach_set_rtc_mmss,
PATCH 10/10 x86 tsc: enumerate BXT tsc_khz via CPUID
In reply to Len BrownFrom: Len Brown <[email protected]>
Hard code the BXT crystal clock (aka ART - Always Running Timer) to 19.200 MHz, and use CPUID leaf 0x15 to determine the BXT TSC frequency.
Use tsc_khz to sanity check BXT cpu_khz,
which can be erroneous in some configurations.
--- arch/x86/kernel/tsc.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-)
arch/x86/kernel/tsc.c +15 -1
@@ -693,7 +693,11 @@ unsigned long native_calibrate_tsc(void)switch (boot_cpu_data.x86_model) {case 0x4E :/* SKL */ case 0x5E :/* SKL */ - crystal_khz =24000 ;/* 24 MHz */ + crystal_khz =24000 ;/* 24.0 MHz */ +break ; +case 0x5C :/* BXT */ + crystal_khz =19200 ;/* 19.2 MHz */ +break ; } }
@@ -895,6 +899,8 @@ int recalibrate_cpu_khz(void) tsc_khz = x86_platform.calibrate_tsc ();if (tsc_khz ==0 ) tsc_khz = cpu_khz; +else if (abs (cpu_khz - tsc_khz) *10 > tsc_khz) + cpu_khz = tsc_khz;cpu_data (0 ).loops_per_jiffy =cpufreq_scale (cpu_data (0 ).loops_per_jiffy, cpu_khz_old, cpu_khz);
@@ -1302,8 +1308,16 @@ void __init tsc_init(void) cpu_khz = x86_platform.calibrate_cpu (); tsc_khz = x86_platform.calibrate_tsc (); + +/* +* Trust non-zero tsc_khz as authorative, +* and use it to sanity check cpu_khz, +* which will be off if system timer is off. +*/ if (tsc_khz ==0 ) tsc_khz = cpu_khz; +else if (abs (cpu_khz - tsc_khz) *10 > tsc_khz) + cpu_khz = tsc_khz;if (!tsc_khz) {mark_tsc_unstable ("could not calculate TSC khz" );
Signature · 1 line
2.9.0
tip-bot for Len Brown
merge bot[tip:x86/timers] x86/tsc: Enumerate BXT tsc_khz via CPUID
x86/tsc: Enumerate BXT tsc_khz via CPUID
Commit-ID: a3dc6a4c9c329bf6ac4ee996c67557664d6b780e Gitweb: http://git.kernel.org/tip/a3dc6a4c9c329bf6ac4ee996c67557664d6b780e Author: Len Brown <[email protected]> AuthorDate: Fri, 17 Jun 2016 01:22:52 -0400 Committer: Ingo Molnar <[email protected]> CommitDate: Sun, 10 Jul 2016 17:00:14 +0200
x86/tsc: Enumerate BXT tsc_khz via CPUID
Hard code the BXT crystal clock (aka ART - Always Running Timer) to 19.200 MHz, and use CPUID leaf 0x15 to determine the BXT TSC frequency.
Use tsc_khz to sanity check BXT cpu_khz,
which can be erroneous in some configurations.
(I simplified the original patch from Bin Gao.)
Original-From: Bin Gao <[email protected]>
--- arch/x86/kernel/tsc.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-)
arch/x86/kernel/tsc.c +15 -1
@@ -693,7 +693,11 @@ unsigned long native_calibrate_tsc(void)switch (boot_cpu_data.x86_model) {case 0x4E :/* SKL */ case 0x5E :/* SKL */ - crystal_khz =24000 ;/* 24 MHz */ + crystal_khz =24000 ;/* 24.0 MHz */ +break ; +case 0x5C :/* BXT */ + crystal_khz =19200 ;/* 19.2 MHz */ +break ; } }
@@ -895,6 +899,8 @@ int recalibrate_cpu_khz(void) tsc_khz = x86_platform.calibrate_tsc ();if (tsc_khz ==0 ) tsc_khz = cpu_khz; +else if (abs (cpu_khz - tsc_khz) *10 > tsc_khz) + cpu_khz = tsc_khz;cpu_data (0 ).loops_per_jiffy =cpufreq_scale (cpu_data (0 ).loops_per_jiffy, cpu_khz_old, cpu_khz);
@@ -1302,8 +1308,16 @@ void __init tsc_init(void) cpu_khz = x86_platform.calibrate_cpu (); tsc_khz = x86_platform.calibrate_tsc (); + +/* +* Trust non-zero tsc_khz as authorative, +* and use it to sanity check cpu_khz, +* which will be off if system timer is off. +*/ if (tsc_khz ==0 ) tsc_khz = cpu_khz; +else if (abs (cpu_khz - tsc_khz) *10 > tsc_khz) + cpu_khz = tsc_khz;if (!tsc_khz) {mark_tsc_unstable ("could not calculate TSC khz" );
tip-bot for Len Brown
merge bot[tip:x86/timers] x86/tsc: Enumerate BXT tsc_khz via CPUID
In reply to Len Brownx86/tsc: Enumerate BXT tsc_khz via CPUID
Commit-ID: ff4c86635ee12461fd3bd911d7d5253394da8f9d Gitweb: http://git.kernel.org/tip/ff4c86635ee12461fd3bd911d7d5253394da8f9d Author: Len Brown <[email protected]> AuthorDate: Fri, 17 Jun 2016 01:22:52 -0400 Committer: Ingo Molnar <[email protected]> CommitDate: Mon, 11 Jul 2016 21:30:13 +0200
x86/tsc: Enumerate BXT tsc_khz via CPUID
Hard code the BXT crystal clock (aka ART - Always Running Timer) to 19.200 MHz, and use CPUID leaf 0x15 to determine the BXT TSC frequency.
Use tsc_khz to sanity check BXT cpu_khz,
which can be erroneous in some configurations.
(I simplified the original patch from Bin Gao.)
Original-From: Bin Gao <[email protected]>
--- arch/x86/kernel/tsc.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-)
arch/x86/kernel/tsc.c +15 -1
@@ -693,7 +693,11 @@ unsigned long native_calibrate_tsc(void)switch (boot_cpu_data.x86_model) {case 0x4E :/* SKL */ case 0x5E :/* SKL */ - crystal_khz =24000 ;/* 24 MHz */ + crystal_khz =24000 ;/* 24.0 MHz */ +break ; +case 0x5C :/* BXT */ + crystal_khz =19200 ;/* 19.2 MHz */ +break ; } }
@@ -895,6 +899,8 @@ int recalibrate_cpu_khz(void) tsc_khz = x86_platform.calibrate_tsc ();if (tsc_khz ==0 ) tsc_khz = cpu_khz; +else if (abs (cpu_khz - tsc_khz) *10 > tsc_khz) + cpu_khz = tsc_khz;cpu_data (0 ).loops_per_jiffy =cpufreq_scale (cpu_data (0 ).loops_per_jiffy, cpu_khz_old, cpu_khz);
@@ -1302,8 +1308,16 @@ void __init tsc_init(void) cpu_khz = x86_platform.calibrate_cpu (); tsc_khz = x86_platform.calibrate_tsc (); + +/* +* Trust non-zero tsc_khz as authorative, +* and use it to sanity check cpu_khz, +* which will be off if system timer is off. +*/ if (tsc_khz ==0 ) tsc_khz = cpu_khz; +else if (abs (cpu_khz - tsc_khz) *10 > tsc_khz) + cpu_khz = tsc_khz;if (!tsc_khz) {mark_tsc_unstable ("could not calculate TSC khz" );
Quoted 7 lines · Len Brown
Originally I wrote this series to increase TSC calibration accuracy and speed, but it now it also includes changes that are mandatory for some systems to work correctly. In particular, the Airmont table entires are already being used in products, and some BXT steppings will fail without the check added by patch 10.
Quoted 8 lines
LKP tested this patch series in early April on top of 4.6-rc1 and found a failure. That failure has been fixed upstream in 4.6 by commit
886123fb3a86
(x86/tsc: Read all ratio bits fromMSR_PLATFORM_INFO)So I have re-based the series on top of 4.7-rc3 to take advantage of that fix, as well as to handle 3 merge conflicts due to intervening upstream commits.
Very nice work and good structured patches!