perf vendor events aarch64: Add JSON metrics for ARM Cortex-A53 Processor

PATCH In review William Cohen 3 participants 8 messages Jan 31, 2018 – Feb 16, 2018

Subsystems (2)

perf events Performance events tooling arm64

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William Cohen

author

2018-01-31 03:28 UTC #0 lore raw

PATCH 1/1 perf vendor events aarch64: Add JSON metrics for ARM Cortex-A53 Processor

Add JSON metrics for ARM Cortex-A53 Processor

Signed-off-by William Cohen <[email protected]>

---
 .../pmu-events/arch/arm64/cortex-a53/branch.json   | 27 +++++++++++
 .../perf/pmu-events/arch/arm64/cortex-a53/bus.json | 22 +++++++++
 .../pmu-events/arch/arm64/cortex-a53/cache.json    | 27 +++++++++++
 .../pmu-events/arch/arm64/cortex-a53/memory.json   | 22 +++++++++
 .../pmu-events/arch/arm64/cortex-a53/other.json    | 32 +++++++++++++
 .../pmu-events/arch/arm64/cortex-a53/pipeline.json | 52 ++++++++++++++++++++++
 tools/perf/pmu-events/arch/arm64/mapfile.csv       |  1 +
 7 files changed, 183 insertions(+)
 create mode 100644 tools/perf/pmu-events/arch/arm64/cortex-a53/branch.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/cortex-a53/bus.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/cortex-a53/cache.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/cortex-a53/memory.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/cortex-a53/other.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/cortex-a53/pipeline.json

tools/perf/pmu-events/arch/arm64/cortex-a53/branch.json new file +27 -0

new file mode 100644
index 000000000000..3b6208763e50
@@ -0,0 +1,27 @@
+[
+  {,
+    "EventCode": "0x7A",
+    "EventName": "BR_INDIRECT_SPEC",
+    "BriefDescription": "Branch speculatively executed - Indirect branch"
+  },
+  {,
+    "EventCode": "0xC9",
+    "EventName": "BR_COND",
+    "BriefDescription": "Conditional branch executed"
+  },
+  {,
+    "EventCode": "0xCA",
+    "EventName": "BR_INDIRECT_MISPRED",
+    "BriefDescription": "Indirect branch mispredicted"
+  },
+  {,
+    "EventCode": "0xCB",
+    "EventName": "BR_INDIRECT_MISPRED_ADDR",
+    "BriefDescription": "Indirect branch mispredicted because of address miscompare"
+  },
+  {,
+    "EventCode": "0xCC",
+    "EventName": "BR_COND_MISPRED",
+    "BriefDescription": "Conditional branch mispredicted"
+  }
+]

tools/perf/pmu-events/arch/arm64/cortex-a53/bus.json new file +22 -0

new file mode 100644
index 000000000000..480d9f7460ab
@@ -0,0 +1,22 @@
+[
+  {,
+    "EventCode": "0x60",
+    "EventName": "BUS_ACCESS_LD",
+    "BriefDescription": "Bus access - Read"
+  },
+  {,
+    "EventCode": "0x61",
+    "EventName": "BUS_ACCESS_ST",
+    "BriefDescription": "Bus access - Write"
+  },
+  {,
+    "EventCode": "0xC0",
+    "EventName": "EXT_MEM_REQ",
+    "BriefDescription": "External memory request"
+  },
+  {,
+    "EventCode": "0xC1",
+    "EventName": "EXT_MEM_REQ_NC",
+    "BriefDescription": "Non-cacheable external memory request"
+  }
+]

tools/perf/pmu-events/arch/arm64/cortex-a53/cache.json new file +27 -0

new file mode 100644
index 000000000000..11baad6344b9
@@ -0,0 +1,27 @@
+[
+  {,
+    "EventCode": "0xC2",
+    "EventName": "PREFETCH_LINEFILL",
+    "BriefDescription": "Linefill because of prefetch"
+  },
+  {,
+    "EventCode": "0xC3",
+    "EventName": "PREFETCH_LINEFILL_DROP",
+    "BriefDescription": "Instruction Cache Throttle occurred"
+  },
+  {,
+    "EventCode": "0xC4",
+    "EventName": "READ_ALLOC_ENTER",
+    "BriefDescription": "Entering read allocate mode"
+  },
+  {,
+    "EventCode": "0xC5",
+    "EventName": "READ_ALLOC",
+    "BriefDescription": "Read allocate mode"
+  },
+  {,
+    "EventCode": "0xC8",
+    "EventName": "EXT_SNOOP",
+    "BriefDescription": "SCU Snooped data from another CPU for this CPU"
+  }
+]

tools/perf/pmu-events/arch/arm64/cortex-a53/memory.json new file +22 -0

new file mode 100644
index 000000000000..480d9f7460ab
@@ -0,0 +1,22 @@
+[
+  {,
+    "EventCode": "0x60",
+    "EventName": "BUS_ACCESS_LD",
+    "BriefDescription": "Bus access - Read"
+  },
+  {,
+    "EventCode": "0x61",
+    "EventName": "BUS_ACCESS_ST",
+    "BriefDescription": "Bus access - Write"
+  },
+  {,
+    "EventCode": "0xC0",
+    "EventName": "EXT_MEM_REQ",
+    "BriefDescription": "External memory request"
+  },
+  {,
+    "EventCode": "0xC1",
+    "EventName": "EXT_MEM_REQ_NC",
+    "BriefDescription": "Non-cacheable external memory request"
+  }
+]

tools/perf/pmu-events/arch/arm64/cortex-a53/other.json new file +32 -0

new file mode 100644
index 000000000000..73a22402d003
@@ -0,0 +1,32 @@
+[
+  {,
+    "EventCode": "0x86",
+    "EventName": "EXC_IRQ",
+    "BriefDescription": "Exception taken, IRQ"
+  },
+  {,
+    "EventCode": "0x87",
+    "EventName": "EXC_FIQ",
+    "BriefDescription": "Exception taken, FIQ"
+  },
+  {,
+    "EventCode": "0xC6",
+    "EventName": "PRE_DECODE_ERR",
+    "BriefDescription": "Pre-decode error"
+  },
+  {,
+    "EventCode": "0xD0",
+    "EventName": "L1I_CACHE_ERR",
+    "BriefDescription": "L1 Instruction Cache (data or tag) memory error"
+  },
+  {,
+    "EventCode": "0xD1",
+    "EventName": "L1D_CACHE_ERR",
+    "BriefDescription": "L1 Data Cache (data, tag or dirty) memory error, correctable or non-correctable"
+  },
+  {,
+    "EventCode": "0xD2",
+    "EventName": "TLB_ERR",
+    "BriefDescription": "TLB memory error"
+  }
+]

tools/perf/pmu-events/arch/arm64/cortex-a53/pipeline.json new file +52 -0

52 lines not on this page · raw message

tools/perf/pmu-events/arch/arm64/mapfile.csv +1 -0

index 219d6756134e..e61c9ca6cf9e 100644
@@ -13,3 +13,4 @@
 #
 #Family-model,Version,Filename,EventType
 0x00000000420f5160,v1,cavium,core
+0x00000000410fd03[[:xdigit:]],v1,cortex-a53,core

Signature · 1 line

2.14.3

Arnaldo Carvalho de Melo

maintainer

2018-02-01 14:43 UTC #1 lore raw

Em Tue, Jan 30, 2018 at 10:28:13PM -0500, William Cohen escreveu:

Quoted 1 line

Add JSON metrics for ARM Cortex-A53 Processor

Hi Will, would it be possible to you include an URL for the document that served as a reference to you to write these files? Did you use some script?

- Arnaldo

Quoted 246 lines

Signed-off-by William Cohen <[email protected]>

---
 .../pmu-events/arch/arm64/cortex-a53/branch.json   | 27 +++++++++++
 .../perf/pmu-events/arch/arm64/cortex-a53/bus.json | 22 +++++++++
 .../pmu-events/arch/arm64/cortex-a53/cache.json    | 27 +++++++++++
 .../pmu-events/arch/arm64/cortex-a53/memory.json   | 22 +++++++++
 .../pmu-events/arch/arm64/cortex-a53/other.json    | 32 +++++++++++++
 .../pmu-events/arch/arm64/cortex-a53/pipeline.json | 52 ++++++++++++++++++++++
 tools/perf/pmu-events/arch/arm64/mapfile.csv       |  1 +
 7 files changed, 183 insertions(+)
 create mode 100644 tools/perf/pmu-events/arch/arm64/cortex-a53/branch.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/cortex-a53/bus.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/cortex-a53/cache.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/cortex-a53/memory.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/cortex-a53/other.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/cortex-a53/pipeline.json

tools/perf/pmu-events/arch/arm64/cortex-a53/branch.json new file +27 -0

new file mode 100644
index 000000000000..3b6208763e50
@@ -0,0 +1,27 @@
+[
+  {,
+    "EventCode": "0x7A",
+    "EventName": "BR_INDIRECT_SPEC",
+    "BriefDescription": "Branch speculatively executed - Indirect branch"
+  },
+  {,
+    "EventCode": "0xC9",
+    "EventName": "BR_COND",
+    "BriefDescription": "Conditional branch executed"
+  },
+  {,
+    "EventCode": "0xCA",
+    "EventName": "BR_INDIRECT_MISPRED",
+    "BriefDescription": "Indirect branch mispredicted"
+  },
+  {,
+    "EventCode": "0xCB",
+    "EventName": "BR_INDIRECT_MISPRED_ADDR",
+    "BriefDescription": "Indirect branch mispredicted because of address miscompare"
+  },
+  {,
+    "EventCode": "0xCC",
+    "EventName": "BR_COND_MISPRED",
+    "BriefDescription": "Conditional branch mispredicted"
+  }
+]

tools/perf/pmu-events/arch/arm64/cortex-a53/bus.json new file +22 -0

new file mode 100644
index 000000000000..480d9f7460ab
@@ -0,0 +1,22 @@
+[
+  {,
+    "EventCode": "0x60",
+    "EventName": "BUS_ACCESS_LD",
+    "BriefDescription": "Bus access - Read"
+  },
+  {,
+    "EventCode": "0x61",
+    "EventName": "BUS_ACCESS_ST",
+    "BriefDescription": "Bus access - Write"
+  },
+  {,
+    "EventCode": "0xC0",
+    "EventName": "EXT_MEM_REQ",
+    "BriefDescription": "External memory request"
+  },
+  {,
+    "EventCode": "0xC1",
+    "EventName": "EXT_MEM_REQ_NC",
+    "BriefDescription": "Non-cacheable external memory request"
+  }
+]

tools/perf/pmu-events/arch/arm64/cortex-a53/cache.json new file +27 -0

new file mode 100644
index 000000000000..11baad6344b9
@@ -0,0 +1,27 @@
+[
+  {,
+    "EventCode": "0xC2",
+    "EventName": "PREFETCH_LINEFILL",
+    "BriefDescription": "Linefill because of prefetch"
+  },
+  {,
+    "EventCode": "0xC3",
+    "EventName": "PREFETCH_LINEFILL_DROP",
+    "BriefDescription": "Instruction Cache Throttle occurred"
+  },
+  {,
+    "EventCode": "0xC4",
+    "EventName": "READ_ALLOC_ENTER",
+    "BriefDescription": "Entering read allocate mode"
+  },
+  {,
+    "EventCode": "0xC5",
+    "EventName": "READ_ALLOC",
+    "BriefDescription": "Read allocate mode"
+  },
+  {,
+    "EventCode": "0xC8",
+    "EventName": "EXT_SNOOP",
+    "BriefDescription": "SCU Snooped data from another CPU for this CPU"
+  }
+]

tools/perf/pmu-events/arch/arm64/cortex-a53/memory.json new file +22 -0

new file mode 100644
index 000000000000..480d9f7460ab
@@ -0,0 +1,22 @@
+[
+  {,
+    "EventCode": "0x60",
+    "EventName": "BUS_ACCESS_LD",
+    "BriefDescription": "Bus access - Read"
+  },
+  {,
+    "EventCode": "0x61",
+    "EventName": "BUS_ACCESS_ST",
+    "BriefDescription": "Bus access - Write"
+  },
+  {,
+    "EventCode": "0xC0",
+    "EventName": "EXT_MEM_REQ",
+    "BriefDescription": "External memory request"
+  },
+  {,
+    "EventCode": "0xC1",
+    "EventName": "EXT_MEM_REQ_NC",
+    "BriefDescription": "Non-cacheable external memory request"
+  }
+]

tools/perf/pmu-events/arch/arm64/cortex-a53/other.json new file +32 -0

new file mode 100644
index 000000000000..73a22402d003
@@ -0,0 +1,32 @@
+[
+  {,
+    "EventCode": "0x86",
+    "EventName": "EXC_IRQ",
+    "BriefDescription": "Exception taken, IRQ"
+  },
+  {,
+    "EventCode": "0x87",
+    "EventName": "EXC_FIQ",
+    "BriefDescription": "Exception taken, FIQ"
+  },
+  {,
+    "EventCode": "0xC6",
+    "EventName": "PRE_DECODE_ERR",
+    "BriefDescription": "Pre-decode error"
+  },
+  {,
+    "EventCode": "0xD0",
+    "EventName": "L1I_CACHE_ERR",
+    "BriefDescription": "L1 Instruction Cache (data or tag) memory error"
+  },
+  {,
+    "EventCode": "0xD1",
+    "EventName": "L1D_CACHE_ERR",
+    "BriefDescription": "L1 Data Cache (data, tag or dirty) memory error, correctable or non-correctable"
+  },
+  {,
+    "EventCode": "0xD2",
+    "EventName": "TLB_ERR",
+    "BriefDescription": "TLB memory error"
+  }
+]

tools/perf/pmu-events/arch/arm64/cortex-a53/pipeline.json new file +52 -0

new file mode 100644
index 000000000000..3149fb90555a
@@ -0,0 +1,52 @@
+[
+  {,
+    "EventCode": "0xC7",
+    "EventName": "STALL_SB_FULL",
+    "BriefDescription": "Data Write operation that stalls the pipeline because the store buffer is full"
+  },
+  {,
+    "EventCode": "0xE0",
+    "EventName": "OTHER_IQ_DEP_STALL",
+    "BriefDescription": "Cycles that the DPU IQ is empty and that is not because of a recent micro-TLB miss, instruction cache miss or pre-decode error"
+  },
+  {,
+    "EventCode": "0xE1",
+    "EventName": "IC_DEP_STALL",
+    "BriefDescription": "Cycles the DPU IQ is empty and there is an instruction cache miss being processed"
+  },
+  {,
+    "EventCode": "0xE2",
+    "EventName": "IUTLB_DEP_STALL",
+    "BriefDescription": "Cycles the DPU IQ is empty and there is an instruction micro-TLB miss being processed"
+  },
+  {,
+    "EventCode": "0xE3",
+    "EventName": "DECODE_DEP_STALL",
+    "BriefDescription": "Cycles the DPU IQ is empty and there is a pre-decode error being processed"
+  },
+  {,
+    "EventCode": "0xE4",
+    "EventName": "OTHER_INTERLOCK_STALL",
+    "BriefDescription": "Cycles there is an interlock other than  Advanced SIMD/Floating-point instructions or load/store instruction"
+  },
+  {,
+    "EventCode": "0xE5",
+    "EventName": "AGU_DEP_STALL",
+    "BriefDescription": "Cycles there is an interlock for a load/store instruction waiting for data to calculate the address in the AGU"
+  },
+  {,
+    "EventCode": "0xE6",
+    "EventName": "SIMD_DEP_STALL",
+    "BriefDescription": "Cycles there is an interlock for an Advanced SIMD/Floating-point operation."
+  },
+  {,
+    "EventCode": "0xE7",
+    "EventName": "LD_DEP_STALL",
+    "BriefDescription": "Cycles there is a stall in the Wr stage because of a load miss"
+  },
+  {,
+    "EventCode": "0xE8",
+    "EventName": "ST_DEP_STALL",
+    "BriefDescription": "Cycles there is a stall in the Wr stage because of a store"
+  }
+]

tools/perf/pmu-events/arch/arm64/mapfile.csv +1 -0

index 219d6756134e..e61c9ca6cf9e 100644
@@ -13,3 +13,4 @@
 #
 #Family-model,Version,Filename,EventType
 0x00000000420f5160,v1,cavium,core
+0x00000000410fd03[[:xdigit:]],v1,cortex-a53,core

Signature · 1 line

2.14.3

William Cohen

author

2018-02-01 15:13 UTC #2 lore raw

Quoted 6 lines · Arnaldo Carvalho de Melo

Em Tue, Jan 30, 2018 at 10:28:13PM -0500, William Cohen escreveu:
Quoted 1 line
Add JSON metrics for ARM Cortex-A53 Processor
Hi Will, would it be possible to you include an URL for the document that served as a reference to you to write these files? Did you use some script?

Hi Arnaldo,

I can certainly add the reference to section "12.9 Events" of the ARM Cortex -A53 MPCore Processor Revision: r0p4 Technical Reference Manual to the patch. That would be useful for people to know where to look for additional information about the events.

Unlike the Intel processors there isn't a script that automatically generated these files. The patch was manually generated from the documentation and the previous oprofile ARM Cortex ac53 event file patch I made.

-Will

Quoted 249 lines

- Arnaldo

Quoted 246 lines

Signed-off-by William Cohen <[email protected]>

---
 .../pmu-events/arch/arm64/cortex-a53/branch.json   | 27 +++++++++++
 .../perf/pmu-events/arch/arm64/cortex-a53/bus.json | 22 +++++++++
 .../pmu-events/arch/arm64/cortex-a53/cache.json    | 27 +++++++++++
 .../pmu-events/arch/arm64/cortex-a53/memory.json   | 22 +++++++++
 .../pmu-events/arch/arm64/cortex-a53/other.json    | 32 +++++++++++++
 .../pmu-events/arch/arm64/cortex-a53/pipeline.json | 52 ++++++++++++++++++++++
 tools/perf/pmu-events/arch/arm64/mapfile.csv       |  1 +
 7 files changed, 183 insertions(+)
 create mode 100644 tools/perf/pmu-events/arch/arm64/cortex-a53/branch.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/cortex-a53/bus.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/cortex-a53/cache.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/cortex-a53/memory.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/cortex-a53/other.json
 create mode 100644 tools/perf/pmu-events/arch/arm64/cortex-a53/pipeline.json

tools/perf/pmu-events/arch/arm64/cortex-a53/branch.json new file +27 -0

new file mode 100644
index 000000000000..3b6208763e50
@@ -0,0 +1,27 @@
+[
+  {,
+    "EventCode": "0x7A",
+    "EventName": "BR_INDIRECT_SPEC",
+    "BriefDescription": "Branch speculatively executed - Indirect branch"
+  },
+  {,
+    "EventCode": "0xC9",
+    "EventName": "BR_COND",
+    "BriefDescription": "Conditional branch executed"
+  },
+  {,
+    "EventCode": "0xCA",
+    "EventName": "BR_INDIRECT_MISPRED",
+    "BriefDescription": "Indirect branch mispredicted"
+  },
+  {,
+    "EventCode": "0xCB",
+    "EventName": "BR_INDIRECT_MISPRED_ADDR",
+    "BriefDescription": "Indirect branch mispredicted because of address miscompare"
+  },
+  {,
+    "EventCode": "0xCC",
+    "EventName": "BR_COND_MISPRED",
+    "BriefDescription": "Conditional branch mispredicted"
+  }
+]

tools/perf/pmu-events/arch/arm64/cortex-a53/bus.json new file +22 -0

new file mode 100644
index 000000000000..480d9f7460ab
@@ -0,0 +1,22 @@
+[
+  {,
+    "EventCode": "0x60",
+    "EventName": "BUS_ACCESS_LD",
+    "BriefDescription": "Bus access - Read"
+  },
+  {,
+    "EventCode": "0x61",
+    "EventName": "BUS_ACCESS_ST",
+    "BriefDescription": "Bus access - Write"
+  },
+  {,
+    "EventCode": "0xC0",
+    "EventName": "EXT_MEM_REQ",
+    "BriefDescription": "External memory request"
+  },
+  {,
+    "EventCode": "0xC1",
+    "EventName": "EXT_MEM_REQ_NC",
+    "BriefDescription": "Non-cacheable external memory request"
+  }
+]

tools/perf/pmu-events/arch/arm64/cortex-a53/cache.json new file +27 -0

new file mode 100644
index 000000000000..11baad6344b9
@@ -0,0 +1,27 @@
+[
+  {,
+    "EventCode": "0xC2",
+    "EventName": "PREFETCH_LINEFILL",
+    "BriefDescription": "Linefill because of prefetch"
+  },
+  {,
+    "EventCode": "0xC3",
+    "EventName": "PREFETCH_LINEFILL_DROP",
+    "BriefDescription": "Instruction Cache Throttle occurred"
+  },
+  {,
+    "EventCode": "0xC4",
+    "EventName": "READ_ALLOC_ENTER",
+    "BriefDescription": "Entering read allocate mode"
+  },
+  {,
+    "EventCode": "0xC5",
+    "EventName": "READ_ALLOC",
+    "BriefDescription": "Read allocate mode"
+  },
+  {,
+    "EventCode": "0xC8",
+    "EventName": "EXT_SNOOP",
+    "BriefDescription": "SCU Snooped data from another CPU for this CPU"
+  }
+]

tools/perf/pmu-events/arch/arm64/cortex-a53/memory.json new file +22 -0

new file mode 100644
index 000000000000..480d9f7460ab
@@ -0,0 +1,22 @@
+[
+  {,
+    "EventCode": "0x60",
+    "EventName": "BUS_ACCESS_LD",
+    "BriefDescription": "Bus access - Read"
+  },
+  {,
+    "EventCode": "0x61",
+    "EventName": "BUS_ACCESS_ST",
+    "BriefDescription": "Bus access - Write"
+  },
+  {,
+    "EventCode": "0xC0",
+    "EventName": "EXT_MEM_REQ",
+    "BriefDescription": "External memory request"
+  },
+  {,
+    "EventCode": "0xC1",
+    "EventName": "EXT_MEM_REQ_NC",
+    "BriefDescription": "Non-cacheable external memory request"
+  }
+]

tools/perf/pmu-events/arch/arm64/cortex-a53/other.json new file +32 -0

new file mode 100644
index 000000000000..73a22402d003
@@ -0,0 +1,32 @@
+[
+  {,
+    "EventCode": "0x86",
+    "EventName": "EXC_IRQ",
+    "BriefDescription": "Exception taken, IRQ"
+  },
+  {,
+    "EventCode": "0x87",
+    "EventName": "EXC_FIQ",
+    "BriefDescription": "Exception taken, FIQ"
+  },
+  {,
+    "EventCode": "0xC6",
+    "EventName": "PRE_DECODE_ERR",
+    "BriefDescription": "Pre-decode error"
+  },
+  {,
+    "EventCode": "0xD0",
+    "EventName": "L1I_CACHE_ERR",
+    "BriefDescription": "L1 Instruction Cache (data or tag) memory error"
+  },
+  {,
+    "EventCode": "0xD1",
+    "EventName": "L1D_CACHE_ERR",
+    "BriefDescription": "L1 Data Cache (data, tag or dirty) memory error, correctable or non-correctable"
+  },
+  {,
+    "EventCode": "0xD2",
+    "EventName": "TLB_ERR",
+    "BriefDescription": "TLB memory error"
+  }
+]

tools/perf/pmu-events/arch/arm64/cortex-a53/pipeline.json new file +52 -0

new file mode 100644
index 000000000000..3149fb90555a
@@ -0,0 +1,52 @@
+[
+  {,
+    "EventCode": "0xC7",
+    "EventName": "STALL_SB_FULL",
+    "BriefDescription": "Data Write operation that stalls the pipeline because the store buffer is full"
+  },
+  {,
+    "EventCode": "0xE0",
+    "EventName": "OTHER_IQ_DEP_STALL",
+    "BriefDescription": "Cycles that the DPU IQ is empty and that is not because of a recent micro-TLB miss, instruction cache miss or pre-decode error"
+  },
+  {,
+    "EventCode": "0xE1",
+    "EventName": "IC_DEP_STALL",
+    "BriefDescription": "Cycles the DPU IQ is empty and there is an instruction cache miss being processed"
+  },
+  {,
+    "EventCode": "0xE2",
+    "EventName": "IUTLB_DEP_STALL",
+    "BriefDescription": "Cycles the DPU IQ is empty and there is an instruction micro-TLB miss being processed"
+  },
+  {,
+    "EventCode": "0xE3",
+    "EventName": "DECODE_DEP_STALL",
+    "BriefDescription": "Cycles the DPU IQ is empty and there is a pre-decode error being processed"
+  },
+  {,
+    "EventCode": "0xE4",
+    "EventName": "OTHER_INTERLOCK_STALL",
+    "BriefDescription": "Cycles there is an interlock other than  Advanced SIMD/Floating-point instructions or load/store instruction"
+  },
+  {,
+    "EventCode": "0xE5",
+    "EventName": "AGU_DEP_STALL",
+    "BriefDescription": "Cycles there is an interlock for a load/store instruction waiting for data to calculate the address in the AGU"
+  },
+  {,
+    "EventCode": "0xE6",
+    "EventName": "SIMD_DEP_STALL",
+    "BriefDescription": "Cycles there is an interlock for an Advanced SIMD/Floating-point operation."
+  },
+  {,
+    "EventCode": "0xE7",
+    "EventName": "LD_DEP_STALL",
+    "BriefDescription": "Cycles there is a stall in the Wr stage because of a load miss"
+  },
+  {,
+    "EventCode": "0xE8",
+    "EventName": "ST_DEP_STALL",
+    "BriefDescription": "Cycles there is a stall in the Wr stage because of a store"
+  }
+]

tools/perf/pmu-events/arch/arm64/mapfile.csv +1 -0

index 219d6756134e..e61c9ca6cf9e 100644
@@ -13,3 +13,4 @@
 #
 #Family-model,Version,Filename,EventType
 0x00000000420f5160,v1,cavium,core
+0x00000000410fd03[[:xdigit:]],v1,cortex-a53,core

Signature · 1 line

2.14.3

Arnaldo Carvalho de Melo

maintainer

2018-02-01 20:51 UTC #3 lore raw

Em Thu, Feb 01, 2018 at 10:12:59AM -0500, William Cohen escreveu:

Quoted 8 lines · Arnaldo Carvalho de Melo

Quoted 6 lines
Em Tue, Jan 30, 2018 at 10:28:13PM -0500, William Cohen escreveu:
Quoted 1 line
Add JSON metrics for ARM Cortex-A53 Processor
Hi Will, would it be possible to you include an URL for the document that served as a reference to you to write these files? Did you use some script?

Quoted 6 lines

Hi Arnaldo,
I can certainly add the reference to section "12.9 Events" of the ARM Cortex -A53 MPCore Processor Revision: r0p4 Technical Reference Manual to the patch. That would be useful for people to know where to look for additional information about the events.

I'll take these clarifications and add it to your patch, that I am applying now, please let me know if you have anything else to add and I'll ammend it if I get it before I send it upstream.

Quoted 4 lines

Unlike the Intel processors there isn't a script that automatically generated these files. The patch was manually generated from the documentation and the previous oprofile ARM Cortex ac53 event file patch I made.

Thanks a lot for this extra information,

- Arnaldo

William Cohen

author

2018-02-01 21:52 UTC #4 lore raw

Quoted 16 lines · Arnaldo Carvalho de Melo

Em Thu, Feb 01, 2018 at 10:12:59AM -0500, William Cohen escreveu:
Quoted 14 lines · Arnaldo Carvalho de Melo
Quoted 6 lines
Em Tue, Jan 30, 2018 at 10:28:13PM -0500, William Cohen escreveu:
Quoted 1 line
Add JSON metrics for ARM Cortex-A53 Processor
Hi Will, would it be possible to you include an URL for the document that served as a reference to you to write these files? Did you use some script?
Hi Arnaldo,
I can certainly add the reference to section "12.9 Events" of the ARM Cortex -A53 MPCore Processor Revision: r0p4 Technical Reference Manual to the patch. That would be useful for people to know where to look for additional information about the events.

Hi Arnaldo,

The ARM Cortex A53 manual is available at:

http://infocenter.arm.com/help/topic/com.arm.doc.ddi0500g/DDI0500G_cortex_a53_trm.pdf

It would probably be useful to include that URL in the commit information to make it easier for people to look up the information.

-Will

Quoted 13 lines

I'll take these clarifications and add it to your patch, that I am applying now, please let me know if you have anything else to add and I'll ammend it if I get it before I send it upstream.
Quoted 4 lines
Unlike the Intel processors there isn't a script that automatically generated these files. The patch was manually generated from the documentation and the previous oprofile ARM Cortex ac53 event file patch I made.
Thanks a lot for this extra information,
- Arnaldo

Arnaldo Carvalho de Melo

maintainer

2018-02-02 13:36 UTC #5 lore raw

Em Thu, Feb 01, 2018 at 04:52:16PM -0500, William Cohen escreveu:

Quoted 18 lines · Arnaldo Carvalho de Melo

Quoted 16 lines
Em Thu, Feb 01, 2018 at 10:12:59AM -0500, William Cohen escreveu:
Quoted 14 lines · Arnaldo Carvalho de Melo
Quoted 6 lines
Em Tue, Jan 30, 2018 at 10:28:13PM -0500, William Cohen escreveu:
Quoted 1 line
Add JSON metrics for ARM Cortex-A53 Processor
Hi Will, would it be possible to you include an URL for the document that served as a reference to you to write these files? Did you use some script?
Hi Arnaldo,
I can certainly add the reference to section "12.9 Events" of the ARM Cortex -A53 MPCore Processor Revision: r0p4 Technical Reference Manual to the patch. That would be useful for people to know where to look for additional information about the events.

Quoted 8 lines

Hi Arnaldo,
The ARM Cortex A53 manual is available at:
http://infocenter.arm.com/help/topic/com.arm.doc.ddi0500g/DDI0500G_cortex_a53_trm.pdf
It would probably be useful to include that URL in the commit information to make it easier for people to look up the information.

Thanks, I'll add that to that cset.

- Arnaldo

Quoted 15 lines

-Will
Quoted 13 lines
I'll take these clarifications and add it to your patch, that I am applying now, please let me know if you have anything else to add and I'll ammend it if I get it before I send it upstream.
Quoted 4 lines
Unlike the Intel processors there isn't a script that automatically generated these files. The patch was manually generated from the documentation and the previous oprofile ARM Cortex ac53 event file patch I made.
Thanks a lot for this extra information,
- Arnaldo

tip-bot for William Cohen

merge bot

2018-02-13 12:15 UTC #6 lore raw

In reply to William Cohen

perf vendor events aarch64: Add JSON metrics for ARM Cortex-A53 Processor

Commit-ID:  109def8f4b73a508de947a33c5965f3aa568aee1
Gitweb:     https://git.kernel.org/tip/109def8f4b73a508de947a33c5965f3aa568aee1
Author:     William Cohen <[email protected]>
AuthorDate: Tue, 30 Jan 2018 22:28:13 -0500
Committer:  Arnaldo Carvalho de Melo <[email protected]>
CommitDate: Tue, 6 Feb 2018 10:11:49 -0300

perf vendor events aarch64: Add JSON metrics for ARM Cortex-A53 Processor

Add JSON metrics for ARM Cortex-A53 Processor.

The relevant documentation is in the "12.9 Events" section of the ARM Cortex A53 MPCore Processor Revision: r0p4 Technical Reference Manual.

The ARM Cortex A53 manual is available at:

http://infocenter.arm.com/help/topic/com.arm.doc.ddi0500g/DDI0500G_cortex_a53_trm.pdf

Use that to look for additional information about the events.

Signed-off-by William Cohen <[email protected]>

Cc Alexander Shishkin <[email protected]>

Cc Jiri Olsa <[email protected]>

Cc Namhyung Kim <[email protected]>

Cc Peter Zijlstra <[email protected]>

Link http://lkml.kernel.org/r/[email protected] open here

[ Added references provided by William Cohen ]

Signed-off-by Arnaldo Carvalho de Melo <[email protected]>

---
 .../pmu-events/arch/arm64/cortex-a53/branch.json   | 27 +++++++++++
 .../perf/pmu-events/arch/arm64/cortex-a53/bus.json | 22 +++++++++
 .../pmu-events/arch/arm64/cortex-a53/cache.json    | 27 +++++++++++
 .../pmu-events/arch/arm64/cortex-a53/memory.json   | 22 +++++++++
 .../pmu-events/arch/arm64/cortex-a53/other.json    | 32 +++++++++++++
 .../pmu-events/arch/arm64/cortex-a53/pipeline.json | 52 ++++++++++++++++++++++
 tools/perf/pmu-events/arch/arm64/mapfile.csv       |  1 +
 7 files changed, 183 insertions(+)

tools/perf/pmu-events/arch/arm64/cortex-a53/branch.json new file +27 -0

new file mode 100644
index 0000000..3b62087
@@ -0,0 +1,27 @@
+[
+  {,
+    "EventCode": "0x7A",
+    "EventName": "BR_INDIRECT_SPEC",
+    "BriefDescription": "Branch speculatively executed - Indirect branch"
+  },
+  {,
+    "EventCode": "0xC9",
+    "EventName": "BR_COND",
+    "BriefDescription": "Conditional branch executed"
+  },
+  {,
+    "EventCode": "0xCA",
+    "EventName": "BR_INDIRECT_MISPRED",
+    "BriefDescription": "Indirect branch mispredicted"
+  },
+  {,
+    "EventCode": "0xCB",
+    "EventName": "BR_INDIRECT_MISPRED_ADDR",
+    "BriefDescription": "Indirect branch mispredicted because of address miscompare"
+  },
+  {,
+    "EventCode": "0xCC",
+    "EventName": "BR_COND_MISPRED",
+    "BriefDescription": "Conditional branch mispredicted"
+  }
+]

tools/perf/pmu-events/arch/arm64/cortex-a53/bus.json new file +22 -0

new file mode 100644
index 0000000..480d9f7
@@ -0,0 +1,22 @@
+[
+  {,
+    "EventCode": "0x60",
+    "EventName": "BUS_ACCESS_LD",
+    "BriefDescription": "Bus access - Read"
+  },
+  {,
+    "EventCode": "0x61",
+    "EventName": "BUS_ACCESS_ST",
+    "BriefDescription": "Bus access - Write"
+  },
+  {,
+    "EventCode": "0xC0",
+    "EventName": "EXT_MEM_REQ",
+    "BriefDescription": "External memory request"
+  },
+  {,
+    "EventCode": "0xC1",
+    "EventName": "EXT_MEM_REQ_NC",
+    "BriefDescription": "Non-cacheable external memory request"
+  }
+]

tools/perf/pmu-events/arch/arm64/cortex-a53/cache.json new file +27 -0

new file mode 100644
index 0000000..11baad6
@@ -0,0 +1,27 @@
+[
+  {,
+    "EventCode": "0xC2",
+    "EventName": "PREFETCH_LINEFILL",
+    "BriefDescription": "Linefill because of prefetch"
+  },
+  {,
+    "EventCode": "0xC3",
+    "EventName": "PREFETCH_LINEFILL_DROP",
+    "BriefDescription": "Instruction Cache Throttle occurred"
+  },
+  {,
+    "EventCode": "0xC4",
+    "EventName": "READ_ALLOC_ENTER",
+    "BriefDescription": "Entering read allocate mode"
+  },
+  {,
+    "EventCode": "0xC5",
+    "EventName": "READ_ALLOC",
+    "BriefDescription": "Read allocate mode"
+  },
+  {,
+    "EventCode": "0xC8",
+    "EventName": "EXT_SNOOP",
+    "BriefDescription": "SCU Snooped data from another CPU for this CPU"
+  }
+]

tools/perf/pmu-events/arch/arm64/cortex-a53/memory.json new file +22 -0

new file mode 100644
index 0000000..480d9f7
@@ -0,0 +1,22 @@
+[
+  {,
+    "EventCode": "0x60",
+    "EventName": "BUS_ACCESS_LD",
+    "BriefDescription": "Bus access - Read"
+  },
+  {,
+    "EventCode": "0x61",
+    "EventName": "BUS_ACCESS_ST",
+    "BriefDescription": "Bus access - Write"
+  },
+  {,
+    "EventCode": "0xC0",
+    "EventName": "EXT_MEM_REQ",
+    "BriefDescription": "External memory request"
+  },
+  {,
+    "EventCode": "0xC1",
+    "EventName": "EXT_MEM_REQ_NC",
+    "BriefDescription": "Non-cacheable external memory request"
+  }
+]

tools/perf/pmu-events/arch/arm64/cortex-a53/other.json new file +32 -0

new file mode 100644
index 0000000..73a2240
@@ -0,0 +1,32 @@
+[
+  {,
+    "EventCode": "0x86",
+    "EventName": "EXC_IRQ",
+    "BriefDescription": "Exception taken, IRQ"
+  },
+  {,
+    "EventCode": "0x87",
+    "EventName": "EXC_FIQ",
+    "BriefDescription": "Exception taken, FIQ"
+  },
+  {,
+    "EventCode": "0xC6",
+    "EventName": "PRE_DECODE_ERR",
+    "BriefDescription": "Pre-decode error"
+  },
+  {,
+    "EventCode": "0xD0",
+    "EventName": "L1I_CACHE_ERR",
+    "BriefDescription": "L1 Instruction Cache (data or tag) memory error"
+  },
+  {,
+    "EventCode": "0xD1",
+    "EventName": "L1D_CACHE_ERR",
+    "BriefDescription": "L1 Data Cache (data, tag or dirty) memory error, correctable or non-correctable"
+  },
+  {,
+    "EventCode": "0xD2",
+    "EventName": "TLB_ERR",
+    "BriefDescription": "TLB memory error"
+  }
+]

tools/perf/pmu-events/arch/arm64/cortex-a53/pipeline.json new file +52 -0

52 lines not on this page · raw message

tools/perf/pmu-events/arch/arm64/mapfile.csv +1 -0

index 219d675..e61c9ca 100644
@@ -13,3 +13,4 @@
 #
 #Family-model,Version,Filename,EventType
 0x00000000420f5160,v1,cavium,core
+0x00000000410fd03[[:xdigit:]],v1,cortex-a53,core

tip-bot for William Cohen

merge bot

2018-02-16 09:51 UTC #7 lore raw

In reply to William Cohen

perf vendor events aarch64: Add JSON metrics for ARM Cortex-A53 Processor

Commit-ID:  0b7c1528fb741803396da68a9d8d285ff7db731c
Gitweb:     https://git.kernel.org/tip/0b7c1528fb741803396da68a9d8d285ff7db731c
Author:     William Cohen <[email protected]>
AuthorDate: Tue, 30 Jan 2018 22:28:13 -0500
Committer:  Arnaldo Carvalho de Melo <[email protected]>
CommitDate: Thu, 15 Feb 2018 09:49:44 -0300

perf vendor events aarch64: Add JSON metrics for ARM Cortex-A53 Processor

Add JSON metrics for ARM Cortex-A53 Processor.

The relevant documentation is in the "12.9 Events" section of the ARM Cortex A53 MPCore Processor Revision: r0p4 Technical Reference Manual.

The ARM Cortex A53 manual is available at:

http://infocenter.arm.com/help/topic/com.arm.doc.ddi0500g/DDI0500G_cortex_a53_trm.pdf

Use that to look for additional information about the events.

Signed-off-by William Cohen <[email protected]>

Cc Alexander Shishkin <[email protected]>

Cc Jiri Olsa <[email protected]>

Cc Namhyung Kim <[email protected]>

Cc Peter Zijlstra <[email protected]>

Link http://lkml.kernel.org/r/[email protected] open here

[ Added references provided by William Cohen ]

Signed-off-by Arnaldo Carvalho de Melo <[email protected]>

---
 .../pmu-events/arch/arm64/cortex-a53/branch.json   | 27 +++++++++++
 .../perf/pmu-events/arch/arm64/cortex-a53/bus.json | 22 +++++++++
 .../pmu-events/arch/arm64/cortex-a53/cache.json    | 27 +++++++++++
 .../pmu-events/arch/arm64/cortex-a53/memory.json   | 22 +++++++++
 .../pmu-events/arch/arm64/cortex-a53/other.json    | 32 +++++++++++++
 .../pmu-events/arch/arm64/cortex-a53/pipeline.json | 52 ++++++++++++++++++++++
 tools/perf/pmu-events/arch/arm64/mapfile.csv       |  1 +
 7 files changed, 183 insertions(+)

tools/perf/pmu-events/arch/arm64/cortex-a53/branch.json new file +27 -0

new file mode 100644
index 0000000..3b62087
@@ -0,0 +1,27 @@
+[
+  {,
+    "EventCode": "0x7A",
+    "EventName": "BR_INDIRECT_SPEC",
+    "BriefDescription": "Branch speculatively executed - Indirect branch"
+  },
+  {,
+    "EventCode": "0xC9",
+    "EventName": "BR_COND",
+    "BriefDescription": "Conditional branch executed"
+  },
+  {,
+    "EventCode": "0xCA",
+    "EventName": "BR_INDIRECT_MISPRED",
+    "BriefDescription": "Indirect branch mispredicted"
+  },
+  {,
+    "EventCode": "0xCB",
+    "EventName": "BR_INDIRECT_MISPRED_ADDR",
+    "BriefDescription": "Indirect branch mispredicted because of address miscompare"
+  },
+  {,
+    "EventCode": "0xCC",
+    "EventName": "BR_COND_MISPRED",
+    "BriefDescription": "Conditional branch mispredicted"
+  }
+]

tools/perf/pmu-events/arch/arm64/cortex-a53/bus.json new file +22 -0

new file mode 100644
index 0000000..480d9f7
@@ -0,0 +1,22 @@
+[
+  {,
+    "EventCode": "0x60",
+    "EventName": "BUS_ACCESS_LD",
+    "BriefDescription": "Bus access - Read"
+  },
+  {,
+    "EventCode": "0x61",
+    "EventName": "BUS_ACCESS_ST",
+    "BriefDescription": "Bus access - Write"
+  },
+  {,
+    "EventCode": "0xC0",
+    "EventName": "EXT_MEM_REQ",
+    "BriefDescription": "External memory request"
+  },
+  {,
+    "EventCode": "0xC1",
+    "EventName": "EXT_MEM_REQ_NC",
+    "BriefDescription": "Non-cacheable external memory request"
+  }
+]

tools/perf/pmu-events/arch/arm64/cortex-a53/cache.json new file +27 -0

new file mode 100644
index 0000000..11baad6
@@ -0,0 +1,27 @@
+[
+  {,
+    "EventCode": "0xC2",
+    "EventName": "PREFETCH_LINEFILL",
+    "BriefDescription": "Linefill because of prefetch"
+  },
+  {,
+    "EventCode": "0xC3",
+    "EventName": "PREFETCH_LINEFILL_DROP",
+    "BriefDescription": "Instruction Cache Throttle occurred"
+  },
+  {,
+    "EventCode": "0xC4",
+    "EventName": "READ_ALLOC_ENTER",
+    "BriefDescription": "Entering read allocate mode"
+  },
+  {,
+    "EventCode": "0xC5",
+    "EventName": "READ_ALLOC",
+    "BriefDescription": "Read allocate mode"
+  },
+  {,
+    "EventCode": "0xC8",
+    "EventName": "EXT_SNOOP",
+    "BriefDescription": "SCU Snooped data from another CPU for this CPU"
+  }
+]

tools/perf/pmu-events/arch/arm64/cortex-a53/memory.json new file +22 -0

new file mode 100644
index 0000000..480d9f7
@@ -0,0 +1,22 @@
+[
+  {,
+    "EventCode": "0x60",
+    "EventName": "BUS_ACCESS_LD",
+    "BriefDescription": "Bus access - Read"
+  },
+  {,
+    "EventCode": "0x61",
+    "EventName": "BUS_ACCESS_ST",
+    "BriefDescription": "Bus access - Write"
+  },
+  {,
+    "EventCode": "0xC0",
+    "EventName": "EXT_MEM_REQ",
+    "BriefDescription": "External memory request"
+  },
+  {,
+    "EventCode": "0xC1",
+    "EventName": "EXT_MEM_REQ_NC",
+    "BriefDescription": "Non-cacheable external memory request"
+  }
+]

tools/perf/pmu-events/arch/arm64/cortex-a53/other.json new file +32 -0

new file mode 100644
index 0000000..73a2240
@@ -0,0 +1,32 @@
+[
+  {,
+    "EventCode": "0x86",
+    "EventName": "EXC_IRQ",
+    "BriefDescription": "Exception taken, IRQ"
+  },
+  {,
+    "EventCode": "0x87",
+    "EventName": "EXC_FIQ",
+    "BriefDescription": "Exception taken, FIQ"
+  },
+  {,
+    "EventCode": "0xC6",
+    "EventName": "PRE_DECODE_ERR",
+    "BriefDescription": "Pre-decode error"
+  },
+  {,
+    "EventCode": "0xD0",
+    "EventName": "L1I_CACHE_ERR",
+    "BriefDescription": "L1 Instruction Cache (data or tag) memory error"
+  },
+  {,
+    "EventCode": "0xD1",
+    "EventName": "L1D_CACHE_ERR",
+    "BriefDescription": "L1 Data Cache (data, tag or dirty) memory error, correctable or non-correctable"
+  },
+  {,
+    "EventCode": "0xD2",
+    "EventName": "TLB_ERR",
+    "BriefDescription": "TLB memory error"
+  }
+]

tools/perf/pmu-events/arch/arm64/cortex-a53/pipeline.json new file +52 -0

52 lines not on this page · raw message

tools/perf/pmu-events/arch/arm64/mapfile.csv +1 -0

index 219d675..e61c9ca 100644
@@ -13,3 +13,4 @@
 #
 #Family-model,Version,Filename,EventType
 0x00000000420f5160,v1,cavium,core
+0x00000000410fd03[[:xdigit:]],v1,cortex-a53,core