Docmentation, ABI: Update contact for L3 cache index disable

PATCH Applied Aravind Gopalakrishnan 4 participants 7 messages May 8, 2015 – May 18, 2015

Subsystems (3)

Stable branch x86 ABI/API

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Aravind Gopalakrishnan

author

2015-05-08 22:38 UTC #0 lore raw

PATCH 1/1 Docmentation, ABI: Update contact for L3 cache index disable

The mailing list [email protected] is now defunct. Using [email protected] in its place.

Signed-off-by Aravind Gopalakrishnan <[email protected]>

---
 Documentation/ABI/testing/sysfs-devices-system-cpu | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Documentation/ABI/testing/sysfs-devices-system-cpu +1 -1

index 99983e6..f1c46d0 100644
@@ -162,7 +162,7 @@ Description:	Discover CPUs in the same CPU frequency coordination domain
 What:		/sys/devices/system/cpu/cpu*/cache/index3/cache_disable_{0,1}
 Date:		August 2008
 KernelVersion:	2.6.27
-Contact:	[email protected]
+Contact:	[email protected]
 Description:	Disable L3 cache indices
 
 		These files exist in every CPU's cache/index3 directory. Each

Signature · 1 line

2.4.0

Borislav Petkov

Applied

2015-05-14 09:25 UTC #1 lore raw

Quoted 13 lines · Aravind Gopalakrishnan

The mailing list [email protected] is now defunct. Using [email protected] in its place.
Signed-off-by Aravind Gopalakrishnan <[email protected]>
---
 Documentation/ABI/testing/sysfs-devices-system-cpu | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
Documentation/ABI/testing/sysfs-devices-system-cpu +0 -0
index 99983e6..f1c46d0 100644

Documentation/ABI/testing/sysfs-devices-system-cpu Description: Discover CPUs in the same CPU frequency coordination domain · line 168

Quoted 8 lines

Documentation/ABI/testing/sysfs-devices-system-cpu +1 -1

@@ -162,7 +162,7 @@ Description:	Discover CPUs in the same CPU frequency coordination domain
 What:		/sys/devices/system/cpu/cpu*/cache/index3/cache_disable_{0,1}
 Date:		August 2008
 KernelVersion:	2.6.27
-Contact:	[email protected]
+Contact:	[email protected]
 Description:	Disable L3 cache indices
 
 		These files exist in every CPU's cache/index3 directory. Each

Applied, thanks.

Signature · 5 lines

Regards/Gruss,
    Boris.

ECO tip #101: Trim your mails when you reply.
--

Borislav Petkov

maintainer

2015-05-18 08:07 UTC #2 lore raw

cover tip queue 2015-05-18

From: Borislav Petkov <[email protected]>

Just two this time, the mce one is urgent material, I've tagged it for stable@.

Aravind Gopalakrishnan (1):
Documentation/ABI: Update contact for L3 cache index disable

Borislav Petkov (1):
x86/mce: Use only critical MCE severity message

Borislav Petkov

maintainer

2015-05-18 08:07 UTC #3 lore raw

PATCH 1/2 Documentation/ABI: Update contact for L3 cache index disable

From: Aravind Gopalakrishnan <[email protected]>

The mailing list [email protected] is now defunct. Use [email protected] in its place.

Signed-off-by Aravind Gopalakrishnan <[email protected]>

Cc [email protected]

Cc Greg KH <[email protected]>

Link http://lkml.kernel.org/r/[email protected] open here

Signed-off-by Borislav Petkov <[email protected]>

---
 Documentation/ABI/testing/sysfs-devices-system-cpu | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Documentation/ABI/testing/sysfs-devices-system-cpu +1 -1

index 99983e67c13c..f1c46d0f5b46 100644
@@ -162,7 +162,7 @@ Description:	Discover CPUs in the same CPU frequency coordination domain
 What:		/sys/devices/system/cpu/cpu*/cache/index3/cache_disable_{0,1}
 Date:		August 2008
 KernelVersion:	2.6.27
-Contact:	[email protected]
+Contact:	[email protected]
 Description:	Disable L3 cache indices
 
 		These files exist in every CPU's cache/index3 directory. Each

Signature · 1 line

2.3.5

tip-bot for Aravind Gopalakrishnan

merge bot

2015-05-18 09:12 UTC #4 lore raw

[tip:x86/urgent] x86/Documentation: Update the contact email for L3 cache index disable functionality

x86/Documentation: Update the contact email for L3 cache index disable functionality

Commit-ID:  ea8e080b604e2c8221af778221d83a59b6529c5b
Gitweb:     http://git.kernel.org/tip/ea8e080b604e2c8221af778221d83a59b6529c5b
Author:     Aravind Gopalakrishnan <[email protected]>
AuthorDate: Mon, 18 May 2015 10:07:16 +0200
Committer:  Ingo Molnar <[email protected]>
CommitDate: Mon, 18 May 2015 10:34:24 +0200

x86/Documentation: Update the contact email for L3 cache index disable functionality

The mailing list [email protected] is now defunct. Use the lkml in its place.

Signed-off-by Aravind Gopalakrishnan <[email protected]>

Signed-off-by Borislav Petkov <[email protected]>

Cc Greg KH <[email protected]>

Cc H. Peter Anvin <[email protected]>

Cc Linus Torvalds <[email protected]>

Cc Peter Zijlstra <[email protected]>

Cc Thomas Gleixner <[email protected]>

Cc [email protected]

Link http://lkml.kernel.org/r/[email protected] open here

[ Changed the contact email to lkml. ]

Signed-off-by Ingo Molnar <[email protected]>

---
 Documentation/ABI/testing/sysfs-devices-system-cpu | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Documentation/ABI/testing/sysfs-devices-system-cpu +1 -1

index 99983e6..da95513 100644
@@ -162,7 +162,7 @@ Description:	Discover CPUs in the same CPU frequency coordination domain
 What:		/sys/devices/system/cpu/cpu*/cache/index3/cache_disable_{0,1}
 Date:		August 2008
 KernelVersion:	2.6.27
-Contact:	[email protected]
+Contact:	Linux kernel mailing list <[email protected]>
 Description:	Disable L3 cache indices
 
 		These files exist in every CPU's cache/index3 directory. Each

Borislav Petkov

maintainer

2015-05-18 08:07 UTC #5 lore raw

PATCH 2/2 x86/mce: Use only critical MCE severity message

In reply to Borislav Petkov

From: Borislav Petkov <[email protected]>

Derek noticed that a critical MCE gets reported with the wrong error message:

[Hardware Error]: CPU 34: Machine Check Exception: 5 Bank 9: f200003f000100b0 [Hardware Error]: RIP !INEXACT! 10:<ffffffff812e14c1> {intel_idle+0xb1/0x170} [Hardware Error]: TSC 49587b8e321cb
[Hardware Error]: PROCESSOR 0:306e4 TIME 1431561296 SOCKET 1 APIC 29 [Hardware Error]: Some CPUs didn't answer in synchronization [Hardware Error]: Machine check: Invalid
^^^^^^^

due to the fact that mce_no_way_out() iterates over all MCA banks and possibly overwrites the @msg argument which is used in the panic printing later.

Change behavior to take the message of only and the (last) critical MCE it detects.

Reported-by Derek <[email protected]>

Signed-off-by Borislav Petkov <[email protected]>

Cc Tony Luck <[email protected]>

Cc <[email protected]>

---
 arch/x86/kernel/cpu/mcheck/mce.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

arch/x86/kernel/cpu/mcheck/mce.c +5 -2

index 521e5016aca6..4d450ac74e3d 100644
@@ -708,6 +708,7 @@ static int mce_no_way_out(struct mce *m, char **msg, unsigned long *validp,
 			  struct pt_regs *regs)
 {
 	int i, ret = 0;
+	char *tmp;
 
 	for (i = 0; i < mca_cfg.banks; i++) {
 		m->status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));

@@ -716,9 +717,11 @@ static int mce_no_way_out(struct mce *m, char **msg, unsigned long *validp,
 			if (quirk_no_way_out)
 				quirk_no_way_out(i, m, regs);
 		}
-		if (mce_severity(m, mca_cfg.tolerant, msg, true) >=
-		    MCE_PANIC_SEVERITY)
+
+		if (mce_severity(m, mca_cfg.tolerant, &tmp, true) >= MCE_PANIC_SEVERITY) {
+			*msg = tmp;
 			ret = 1;
+		}
 	}
 	return ret;
 }

Signature · 1 line

2.3.5

tip-bot for Borislav Petkov

merge bot

2015-05-18 09:12 UTC #6 lore raw

[tip:x86/urgent] x86/mce: Fix MCE severity messages

x86/mce: Fix MCE severity messages

Commit-ID:  17fea54bf0ab34fa09a06bbde2f58ed7bbdf9299
Gitweb:     http://git.kernel.org/tip/17fea54bf0ab34fa09a06bbde2f58ed7bbdf9299
Author:     Borislav Petkov <[email protected]>
AuthorDate: Mon, 18 May 2015 10:07:17 +0200
Committer:  Ingo Molnar <[email protected]>
CommitDate: Mon, 18 May 2015 10:31:22 +0200

x86/mce: Fix MCE severity messages

Derek noticed that a critical MCE gets reported with the wrong error type description:

				   ^^^^^^^

The last line with 'Invalid' should have printed the high level MCE error type description we get from mce_severity, i.e. something like:

[Hardware Error]: Machine check: Action required: data load error in a user process

this happens due to the fact that mce_no_way_out() iterates over all MCA banks and possibly overwrites the @msg argument which is used in the panic printing later.

Change behavior to take the message of only and the (last) critical MCE it detects.

Reported-by Derek <[email protected]>

Signed-off-by Borislav Petkov <[email protected]>

Cc <[email protected]>

Cc H. Peter Anvin <[email protected]>

Cc Linus Torvalds <[email protected]>

Cc Peter Zijlstra <[email protected]>

Cc Thomas Gleixner <[email protected]>

Cc Tony Luck <[email protected]>

Link http://lkml.kernel.org/r/[email protected] open here

Signed-off-by Ingo Molnar <[email protected]>

---
 arch/x86/kernel/cpu/mcheck/mce.c | 7 +++++--
 1 file changed, 5 insertions(+), 2 deletions(-)

arch/x86/kernel/cpu/mcheck/mce.c +5 -2

index e535533..20190bd 100644
@@ -708,6 +708,7 @@ static int mce_no_way_out(struct mce *m, char **msg, unsigned long *validp,
 			  struct pt_regs *regs)
 {
 	int i, ret = 0;
+	char *tmp;
 
 	for (i = 0; i < mca_cfg.banks; i++) {
 		m->status = mce_rdmsrl(MSR_IA32_MCx_STATUS(i));

@@ -716,9 +717,11 @@ static int mce_no_way_out(struct mce *m, char **msg, unsigned long *validp,
 			if (quirk_no_way_out)
 				quirk_no_way_out(i, m, regs);
 		}
-		if (mce_severity(m, mca_cfg.tolerant, msg, true) >=
-		    MCE_PANIC_SEVERITY)
+
+		if (mce_severity(m, mca_cfg.tolerant, &tmp, true) >= MCE_PANIC_SEVERITY) {
+			*msg = tmp;
 			ret = 1;
+		}
 	}
 	return ret;
 }