perf/x86: fixes and improvements for Intel Atom PEBS/LBR support

This short series fixes breakage of Intel Atom PEBS and LBR support in recent kernels. The problems were introduced with the changes in the PEBS logic to handle deeper buffer. Refer to the changelog in the specific commits for SHA1.

The first patch fixes LBR assumption that 64-bit LBR format implies LBR_SELECT msr. The second patch fixes PEBS support and wrong pointer arithmetic and assumption about Atom/Core2 PEBS record layout.

The third patch adds an alias for cycles:pp to Intel Atom given that perf record/top uses cycles:pp nowadays.

The fourth patch allows using precise sampling attribute on all events on Intel Atom. When used on non-PEBS events, no samples are generated. No error is reported, this is consistent with the behavior for other Intel processors.

In V2, we removed the alias function specific to Atom use use the one from Core2 because it is identical as suggested by Kan Liang.

In V3, we split up the series into 4 patches and referenced the commits which introduced the issues.

Stephane Eranian (4):
perf/x86: fix LBR issues on Intel Atom
perf/x86: fix PEBS issues on Intel Atom/Core2 perf/x86: enable cycles:pp for Intel Atom perf/x86: allow precise mode on all events for Intel Atom

 arch/x86/kernel/cpu/perf_event_intel.c     |  1 +
 arch/x86/kernel/cpu/perf_event_intel_ds.c  | 11 ++++++++++-
 arch/x86/kernel/cpu/perf_event_intel_lbr.c | 11 +++++++----
 3 files changed, 18 insertions(+), 5 deletions(-)

1.9.1

This patches fixes the LBR kernel crashes on Intel Atom.

The kernel was assuming that if the CPU supports 64-bit format LBR, then it has an LBR_SELECT MSR. Atom uses 64-bit LBR format but does not have LBR_SELECT. That was causing NULL pointer dereferences in a couple of places.

---
 arch/x86/kernel/cpu/perf_event_intel_lbr.c | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

index e2fad0c..1390148 100644
@@ -161,7 +161,7 @@ static void __intel_pmu_lbr_enable(bool pmi)
 	 */
 	if (cpuc->lbr_sel)
 		lbr_select = cpuc->lbr_sel->config & x86_pmu.lbr_sel_mask;
-	if (!pmi)
+	if (!pmi && cpuc->lbr_sel)
 		wrmsrl(MSR_LBR_SELECT, lbr_select);
 
 	rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);

@@ -430,7 +430,7 @@ static void intel_pmu_lbr_read_32(struct cpu_hw_events *cpuc)
  */
 static void intel_pmu_lbr_read_64(struct cpu_hw_events *cpuc)
 {
-	bool need_info = !(cpuc->lbr_sel->config & LBR_NO_INFO);
+	bool need_info = false;
 	unsigned long mask = x86_pmu.lbr_nr - 1;
 	int lbr_format = x86_pmu.intel_cap.lbr_format;
 	u64 tos = intel_pmu_lbr_tos();

@@ -438,8 +438,11 @@ static void intel_pmu_lbr_read_64(struct cpu_hw_events *cpuc)
 	int out = 0;
 	int num = x86_pmu.lbr_nr;
 
-	if (cpuc->lbr_sel->config & LBR_CALL_STACK)
-		num = tos;
+	if (cpuc->lbr_sel) {
+		need_info = !(cpuc->lbr_sel->config & LBR_NO_INFO);
+		if (cpuc->lbr_sel->config & LBR_CALL_STACK)
+			num = tos;
+	}
 
 	for (i = 0; i < num; i++) {
 		unsigned long lbr_idx = (tos - i) & mask;

1.9.1

This patch fixes broken PEBS support on Intel Atom and Core2 due to wrong pointer arithmetic in intel_pmu_drain_pebs_core().

The get_next_pebs_record_by_bit() was called on PEBS format fmt0 which does not use the pebs_record_nhm layout.

---
 arch/x86/kernel/cpu/perf_event_intel_ds.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

index 5db1c77..dae5f93 100644
@@ -1101,6 +1101,13 @@ get_next_pebs_record_by_bit(void *base, void *top, int bit)
 	void *at;
 	u64 pebs_status;
 
+	/*
+	 * fmt0 does not have a status bitfield (does not use
+	 * perf_record_nhm format)
+	 */
+	if (x86_pmu.intel_cap.pebs_format < 1)
+		return base;
+
 	if (base == NULL)
 		return NULL;
 

@@ -1186,7 +1193,7 @@ static void intel_pmu_drain_pebs_core(struct pt_regs *iregs)
 	if (!event->attr.precise_ip)
 		return;
 
-	n = (top - at) / x86_pmu.pebs_record_size;
+	n = top - at;
 	if (n <= 0)
 		return;
 

1.9.1