perf, x86: Add new stalled cycles events for Intel and AMD CPUs
Subsystems (2)
Commit-ID: 91fc4cc00099986bc1ba50e1f421c3548cffae42 Gitweb: http://git.kernel.org/tip/91fc4cc00099986bc1ba50e1f421c3548cffae42 Author: Ingo Molnar <[email protected]> AuthorDate: Fri, 29 Apr 2011 14:17:19 +0200 Committer: Ingo Molnar <[email protected]> CommitDate: Fri, 29 Apr 2011 14:24:15 +0200
perf, x86: Add new stalled cycles events for Intel and AMD CPUs
Extend the Intel and AMD event definitions with generic front-end and back-end stall events.
( These are only approximations - suggestions are welcome for better events. )
Cc Peter Zijlstra <[email protected]>
Cc Arnaldo Carvalho de Melo <[email protected]>
Cc Frederic Weisbecker <[email protected]>
Signed-off-by Ingo Molnar <[email protected]>
--- arch/x86/kernel/cpu/perf_event_amd.c | 14 ++++++++------ arch/x86/kernel/cpu/perf_event_intel.c | 4 +++- 2 files changed, 11 insertions(+), 7 deletions(-)
arch/x86/kernel/cpu/perf_event_amd.c +8 -6
@@ -96,12 +96,14 @@ static __initconst const u64 amd_hw_cache_event_ids*/ static const u64 amd_perfmon_event_map[] = { - [PERF_COUNT_HW_CPU_CYCLES ] =0x0076 , - [PERF_COUNT_HW_INSTRUCTIONS ] =0x00c0 , - [PERF_COUNT_HW_CACHE_REFERENCES ] =0x0080 , - [PERF_COUNT_HW_CACHE_MISSES ] =0x0081 , - [PERF_COUNT_HW_BRANCH_INSTRUCTIONS ] =0x00c2 , - [PERF_COUNT_HW_BRANCH_MISSES ] =0x00c3 , + [PERF_COUNT_HW_CPU_CYCLES ] =0x0076 , + [PERF_COUNT_HW_INSTRUCTIONS ] =0x00c0 , + [PERF_COUNT_HW_CACHE_REFERENCES ] =0x0080 , + [PERF_COUNT_HW_CACHE_MISSES ] =0x0081 , + [PERF_COUNT_HW_BRANCH_INSTRUCTIONS ] =0x00c2 , + [PERF_COUNT_HW_BRANCH_MISSES ] =0x00c3 , + [PERF_COUNT_HW_STALLED_CYCLES_FRONTEND ] =0x00d0 ,/* "Decoder empty" event */ + [PERF_COUNT_HW_STALLED_CYCLES_BACKEND ] =0x00d1 ,/* "Dispatch stalls" event */ };static u64 amd_pmu_event_map (int hw_event)
arch/x86/kernel/cpu/perf_event_intel.c +3 -1
@@ -1413,7 +1413,9 @@ static __init int intel_pmu_init(void) x86_pmu.enable_all = intel_pmu_nhm_enable_all; x86_pmu.extra_regs = intel_nehalem_extra_regs; -/* Install the stalled-cycles event: UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */ +/* UOPS_ISSUED.STALLED_CYCLES */ + intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_FRONTEND ] =0x180010e ; +/* UOPS_EXECUTED.CORE_ACTIVE_CYCLES,c=1,i=1 */ intel_perfmon_event_map[PERF_COUNT_HW_STALLED_CYCLES_BACKEND ] =0x1803fb1 ;if (ebx &0x40 ) {