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x86/cpu: Correct small issues in P4 erratum 037 code

PATCH New Borislav Petkov 2 participants 2 messages May 8, 2016 – May 10, 2016 x86

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Borislav Petkov

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PATCH 1/1 x86/cpu: Correct small issues in P4 erratum 037 code

From: Borislav Petkov <[email protected]>

Remove the linebreak in the conditional and s/errata/erratum/ as the singular is "erratum".

No functionality change.

Signed-off-by Borislav Petkov <[email protected]>
---
 arch/x86/kernel/cpu/intel.c | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)
arch/x86/kernel/cpu/intel.c +3 -4
index fcc0996afc9f..df9b912ff0fa 100644
@@ -263,15 +263,14 @@ static void intel_workarounds(struct cpuinfo_x86 *c)
 	}
 
 	/*
-	 * P4 Xeon errata 037 workaround.
+	 * P4 Xeon erratum 037 workaround.
 	 * Hardware prefetcher may cause stale data to be loaded into the cache.
 	 */
 	if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) {
 		if (msr_set_bit(MSR_IA32_MISC_ENABLE,
-				MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT)
-		    > 0) {
+				MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) > 0) {
 			pr_info("CPU: C0 stepping P4 Xeon detected.\n");
-			pr_info("CPU: Disabling hardware prefetching (Errata 037)\n");
+			pr_info("CPU: Disabling hardware prefetching (Erratum 037)\n");
 		}
 	}
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2.7.3
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#1 lore raw

[tip:x86/cpu] x86/cpu: Correct comments and messages in P4 erratum 037 handling code

x86/cpu: Correct comments and messages in P4 erratum 037 handling code
Commit-ID:  f0133acc7d4835cfbb86393b7d2a4fba7519585b
Gitweb:     http://git.kernel.org/tip/f0133acc7d4835cfbb86393b7d2a4fba7519585b
Author:     Borislav Petkov <[email protected]>
AuthorDate: Sun, 8 May 2016 20:58:40 +0200
Committer:  Ingo Molnar <[email protected]>
CommitDate: Tue, 10 May 2016 10:05:03 +0200

x86/cpu: Correct comments and messages in P4 erratum 037 handling code

Remove the linebreak in the conditional and s/errata/erratum/ as the singular is "erratum".

No functionality change.

Signed-off-by Borislav Petkov <[email protected]>
Cc Andy Lutomirski <[email protected]>
Cc Borislav Petkov <[email protected]>
Cc Brian Gerst <[email protected]>
Cc Denys Vlasenko <[email protected]>
Cc H. Peter Anvin <[email protected]>
Cc Linus Torvalds <[email protected]>
Cc Peter Zijlstra <[email protected]>
Cc Thomas Gleixner <[email protected]>
Link http://lkml.kernel.org/r/[email protected] open here
Signed-off-by Ingo Molnar <[email protected]>
---
 arch/x86/kernel/cpu/intel.c | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)
arch/x86/kernel/cpu/intel.c +3 -4
index f71a349..5354080 100644
@@ -263,15 +263,14 @@ static void intel_workarounds(struct cpuinfo_x86 *c)
 	}
 
 	/*
-	 * P4 Xeon errata 037 workaround.
+	 * P4 Xeon erratum 037 workaround.
 	 * Hardware prefetcher may cause stale data to be loaded into the cache.
 	 */
 	if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) {
 		if (msr_set_bit(MSR_IA32_MISC_ENABLE,
-				MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT)
-		    > 0) {
+				MSR_IA32_MISC_ENABLE_PREFETCH_DISABLE_BIT) > 0) {
 			pr_info("CPU: C0 stepping P4 Xeon detected.\n");
-			pr_info("CPU: Disabling hardware prefetching (Errata 037)\n");
+			pr_info("CPU: Disabling hardware prefetching (Erratum 037)\n");
 		}
 	}