target-ppc: add Altivec logical operations.
Status from this message: Thanks, applied.
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Patches in v1 Applied
| # | Subject and files | Size | Replies | Applied |
|---|---|---|---|---|
| 1/42 | target-ppc: add Altivec logical operations.target-ppc/ | +18 | 3 replies | |
| 2/42 | target-ppc: add helper macros for later patches.target-ppc/ | +33 | 2 replies | |
| 3/42 | target-ppc: add gen_avr_ptr function.target-ppc/ | +7 | 4 replies | |
| 4/42 | target-ppc: add GEN_VXFORM macro for subsequent instructions.target-ppc/ | +17 | 0 replies | |
| 5/42 | target-ppc: add v{add, sub}u{b, h, w}m instructions.target-ppc/ target-ppc/ target-ppc/ | +33 | 0 replies | |
| 6/42 | target-ppc: add signed fields to ppc_avr_t.target-ppc/ | +3 | 1 reply | |
| 7/42 | target-ppc: add vavg{s, u}{b, h, w} instructions.target-ppc/ target-ppc/ target-ppc/ | +30 | 0 replies | |
| 8/42 | target-ppc: add v{min, max}{s, u}{b, h, w} instructions.target-ppc/ target-ppc/ target-ppc/ | +47 | 0 replies | |
| 9/42 | target-ppc: add GEN_VXRFORM{, 1} macros for subsequent instructions.target-ppc/ | +27 | 0 replies | |
| 10/42 | target-ppc: add vcmpequ{b, h, w} and vcmpgt{s, u}{b, h, w} instructions.target-ppc/ target-ppc/ target-ppc/ | +52 | 0 replies | |
| 11/42 | target-ppc: add vscr access macros.target-ppc/ | +7 | 0 replies | |
| 12/42 | target-ppc: add vmrg{l, h}{b, h, w} instructions.target-ppc/ target-ppc/ target-ppc/ | +47 | 0 replies | |
| 13/42 | target-ppc: add vmul{e, o}{s, u}{b, h} instructions.target-ppc/ target-ppc/ target-ppc/ | +38 | 0 replies | |
| 14/42 | target-ppc: add vsr{, a}{b, h, w} instructions.target-ppc/ target-ppc/ target-ppc/ | +29 | 0 replies | |
| 15/42 | target-ppc: add vsl{b, h, w} instructions.target-ppc/ target-ppc/ target-ppc/ | +20 | 0 replies | |
| 16/42 | target-ppc: add vs{l,r}o instructions.target-ppc/ target-ppc/ target-ppc/ | +31 | 0 replies | |
| 17/42 | target-ppc: add v{add, sub}cuw instructions.target-ppc/ target-ppc/ target-ppc/ | +18 | 0 replies | |
| 18/42 | target-ppc: add lvs{l,r} instructions.target-ppc/ target-ppc/ target-ppc/ | +52 | 0 replies | |
| 19/42 | target-ppc: add m{f, t}vscr instructions.target-ppc/ | +41 | 0 replies | |
| 20/42 | target-ppc: add v{add, sub}{s, u}{b, h, w}s instructions.target-ppc/ target-ppc/ target-ppc/ | +69 | 0 replies | |
| 21/42 | target-ppc: add vrl{b, h, w} instructions.target-ppc/ target-ppc/ target-ppc/ | +20 | 0 replies | |
| 22/42 | target-ppc: add vs{l,r} instructions.target-ppc/ target-ppc/ target-ppc/ | +39 | 0 replies | |
| 23/42 | target-ppc: add vsldoi instruction.target-ppc/ target-ppc/ target-ppc/ | +50 | 0 replies | |
| 24/42 | target-ppc: add GEN_VXFORM_SIMM macro for subsequent instructions.target-ppc/ | +18 | 0 replies | |
| 25/42 | target-ppc: add vspltis{b, h, w} instructions.target-ppc/ target-ppc/ target-ppc/ | +23 | 0 replies | |
| 26/42 | target-ppc: add GEN_VXFORM_UIMM macro for subsequent instructions.target-ppc/ | +20 | 0 replies | |
| 27/42 | target-ppc: add vsplt{b, h, w} instructions.target-ppc/ target-ppc/ target-ppc/ | +29 | 0 replies | |
| 28/42 | target-ppc: add GEN_VXFORM_NOA macro for subsequent instructions.target-ppc/ | +15 | 0 replies | |
| 29/42 | target-ppc: add vupk{h, l}px instructions.target-ppc/ target-ppc/ target-ppc/ | +32 | 0 replies | |
| 30/42 | target-ppc: add vupk{h, l}s{b, h} instructions.target-ppc/ target-ppc/ target-ppc/ | +30 | 0 replies | |
| 31/42 | target-ppc: add GEN_VAFORM_PAIRED macro for subsequent instructions.target-ppc/ | +23 | 0 replies | |
| 32/42 | target-ppc: add vmsum{u, m}bm instructions.target-ppc/ target-ppc/ target-ppc/ | +32 | 0 replies | |
| 33/42 | target-ppc: add vsel and vperm instructions.target-ppc/ target-ppc/ target-ppc/ | +29 | 0 replies | |
| 34/42 | target-ppc: add saturating arithmetic conversion functions for subsequent instructions.target-ppc/ | +27 | 0 replies | |
| 35/42 | target-ppc: add vpks{h, w}{s, u}s, vpku{h, w}us, and vpku{h, w}um instructions.target-ppc/ target-ppc/ target-ppc/ | +51 | 0 replies | |
| 36/42 | target-ppc: add vpkpx instruction.target-ppc/ target-ppc/ target-ppc/ | +21 | 0 replies | |
| 37/42 | target-ppc: add vmh{, r}addshs instructions.target-ppc/ target-ppc/ target-ppc/ | +33 | 0 replies | |
| 38/42 | target-ppc: add vmsumuh{m, s} instructions.target-ppc/ target-ppc/ target-ppc/ | +37 | 0 replies | |
| 39/42 | target-ppc: add vmsumsh{m, s} instructions.target-ppc/ target-ppc/ target-ppc/ | +37 | 0 replies | |
| 40/42 | target-ppc: add vmladduhm instruction.target-ppc/ target-ppc/ target-ppc/ | +28 | 0 replies | |
| 41/42 | target-ppc: add {l, st}ve{b, h, w}x instructions.target-ppc/ target-ppc/ target-ppc/ | +88 | 0 replies | |
| 42/42 | target-ppc: add vsumsws, vsum2sws, and vsum4{sbs, shs, ubs} instructions.target-ppc/ target-ppc/ target-ppc/ | +112 | 0 replies |
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