spi: spi-fsl-spi: Make spi-fsl-spi usable in cpu mode outside of FSL SOC environments and add a grlib variant normally running on sparc

Changes since v3:
- Patches 1-7: Added Acked-by: Anton Vorontsov <[email protected]>
- Patch 1: Small style tweak lining up function arguments properly
- Patch 7: Changed a style issue with two variables declared on same line
- Patch 7: Removed usage of cs_gpio_flags variable to apply cleanly to spi/next
- Patch 7: Changed get_named_gpio "hole value" to -ENOENT => Requries the "spi: Initialize cs_gpio and cs_gpios with ENOENT" patch for TYPE_GRLIB support

Patch 1-6 are ready to be applied
Patch 7 waits for depencency as described above

This makes the cpu mode of the driver available outside of an FSL SOC and even powerpc environment. Furthermore, this adds support for the mostly register-compatible SPICTRL core from the GRLIB VHDL IP core library normally running on SPARC.

This effort is split up in several patches for clarity of what is being changed. Patches 3-5 prepares for the introduction of the GRLIB SPICTRL functionality in patch 6.

To use what is introduced right away they could eventually be merged:
Patch A: patch 1
Patch B: patch 2
Patch C: patches 3-6 merged
Patch D: patch 7

Patch 1 makes the driver compileable and presumably useable outside of FSL SOC and powerpc environments (SPARC in particular)

Patch 2 fixes a bug that can happen when a device uses SPI_CS_HIGH

Patches 3-6 makes the driver working for GRLIB SPICTRL cores that has the built in slave select register and that uses that exclusively for chipselects.

Patch 7 introduces gpio support for GRLIB SPICTRL cores. For TYPE_GRLIB support to work properly, patch 7 (and patch 7 only) relies upon the "spi: Initialize cs_gpio and cs_gpios with -ENOENT" patch. This issue does not affect TYPE_FSL at all.

The GRLIB type has been tested under sparc. The FSL type has been compile tested in powerpc, arm and x86 environments. It would be great if someone with an FSL board could test this out.

One could argue that it would be better to add the GRLIB variant as a mode flag in of_mpc8xxx_spi_probe instead of using a new type field, but that would require to add a flag for this core in include/linux/fsl_devices.h which does not feel right given that this core is not part of an FSL device.

Andreas Larsson (7):
spi: spi-fsl-spi: Make driver usable in CPU mode outside of an
FSL_SOC environment
spi: spi-fsl-spi: Make sure in spi_fsl_setup that chipselect becomes
inactive
spi: spi-fsl-spi: Move setting non-zero tx and rx shifts to a
function accessed by a function pointer
spi: spi-fsl-spi: Introduce a type for the driver
spi: spi-fsl-spi: Add support for setting a maximum number of bits
per word
spi: spi-fsl-spi: Add support for Aeroflex Gaisler GRLIB cores
normally running on SPARC
spi: spi-fsl-spi: Add support for gpio chipselects for GRLIB type
cores

 Documentation/devicetree/bindings/spi/fsl-spi.txt  |    3 +-
 .../devicetree/bindings/vendor-prefixes.txt        |    1 +
 drivers/spi/Kconfig                                |   11 +-
 drivers/spi/Makefile                               |    1 +
 drivers/spi/spi-fsl-cpm.c                          |  387 +++++++++++++
 drivers/spi/spi-fsl-cpm.h                          |   43 ++
 drivers/spi/spi-fsl-lib.c                          |    8 +
 drivers/spi/spi-fsl-lib.h                          |   15 +-
 drivers/spi/spi-fsl-spi.c                          |  605 ++++++--------------
 drivers/spi/spi-fsl-spi.h                          |   72 +++
 10 files changed, 722 insertions(+), 424 deletions(-)
 create mode 100644 drivers/spi/spi-fsl-cpm.c
 create mode 100644 drivers/spi/spi-fsl-cpm.h
 create mode 100644 drivers/spi/spi-fsl-spi.h