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Haswell unclaimed register fixes and power well enabling

Paulo Zanoni intel-gfx 1 version Applied

Status from this message: Queued for -next, thanks for the patch.

Get series with b4
b4 am [email protected]

Versions newest first

  1. v1 Latest10 patches 23 repliesApplied

Patches in v1 Applied

#Subject and filesSizeRepliesApplied
1/10drm/i915: don't save/restore DSPARB on gen5+drivers/gpu/drm/i915/i915_suspend.c+4 -22 replies
2/10drm/i915: don't read DP_TP_STATUS(PORT_A)drivers/gpu/drm/i915/intel_dp.c+6 -31 reply
3/10drm/i915: fix intel_init_power_wellsdrivers/gpu/drm/i915/i915_reg.h drivers/gpu/drm/i915/intel_display.c drivers/gpu/drm/i915/intel_drv.h +1 more+59 -265 replies
4/10drm/i915: dynamic Haswell display power well supportdrivers/gpu/drm/i915/intel_ddi.c drivers/gpu/drm/i915/intel_display.c drivers/gpu/drm/i915/intel_drv.h +1 more+40 -21 reply
5/10drm/i915: only disable enabled planes on intel_fb_restore_modedrivers/gpu/drm/i915/intel_fb.c+2 -10 replies
6/10drm/i915: check the power down well on assert_pipe()drivers/gpu/drm/i915/intel_display.c+9 -37 replies
7/10drm/i915: turn on the power well before suspendingdrivers/gpu/drm/i915/i915_drv.c+2 -01 reply
8/10drm/i915: set TRANSCODER_EDP even earlierdrivers/gpu/drm/i915/intel_display.c+5 -51 reply
9/10drm/i915: print IVB/HSW display error interruptsdrivers/gpu/drm/i915/i915_irq.c drivers/gpu/drm/i915/i915_reg.h+76 -33 replies
10/10drm/i915: remove "unclaimed register" checks from I915_WRITEdrivers/gpu/drm/i915/i915_drv.c drivers/gpu/drm/i915/i915_irq.c+1 -92 replies

Reviews trailers per patch

6 of 10 patches have a Reviewed-by or Acked-by.

PatchBen WidawskyJani Nikula
1/10R-b
2/10
3/10R-b
4/10R-b
5/10
6/10
7/10R-b
8/10R-b
9/10R-b R-b
10/10

Trailers given in replies are filled; those carried in the patches from earlier versions are outlined with dashes.

Read the v1 thread

Cover letter [PATCH 00/10] Haswell unclaimed register fixes and power well enabling

From: Paulo Zanoni <[email protected]>

Hi

This series fixes a few of our current "unclaimed register" messages, then it introduces the code to disable the power well when we're using eDP only, and then it fixes a few more "unclaimed register" messages brought by the power down code. In the last patches we remove the GEN7_ERR_INT checking from I915_WRITE and move it to the interrupt code.

Quoted 1 line

From my tests, after this series I still only see 1 "unclaimed register" message

that seems to be caused by our driver. All the other messages (there are a lot of messages that happen all together when booting) stop when we blacklist snd_hda_intel and its friends. Still, the plan is to get rid of all the remaining messages.

Cheers,
Paulo

Daniel Vetter (1):
drm/i915: dynamic Haswell display power well support

Paulo Zanoni (9):
drm/i915: don't save/restore DSPARB on gen5+ drm/i915: don't read DP_TP_STATUS(PORT_A)
drm/i915: fix intel_init_power_wells
drm/i915: only disable enabled planes on intel_fb_restore_mode drm/i915: check the power down well on assert_pipe() drm/i915: turn on the power well before suspending drm/i915: set TRANSCODER_EDP even earlier
drm/i915: print IVB/HSW display error interrupts drm/i915: remove "unclaimed register" checks from I915_WRITE

 drivers/gpu/drm/i915/i915_drv.c      |   10 +----
 drivers/gpu/drm/i915/i915_irq.c      |   56 ++++++++++++++++++++++++++-
 drivers/gpu/drm/i915/i915_reg.h      |   31 ++++++++++++---
 drivers/gpu/drm/i915/i915_suspend.c  |    6 ++-
 drivers/gpu/drm/i915/intel_ddi.c     |    8 +++-
 drivers/gpu/drm/i915/intel_display.c |   58 ++++++++++++++++++++++------
 drivers/gpu/drm/i915/intel_dp.c      |    9 +++--
 drivers/gpu/drm/i915/intel_drv.h     |    3 +-
 drivers/gpu/drm/i915/intel_fb.c      |    3 +-
 drivers/gpu/drm/i915/intel_pm.c      |   70 +++++++++++++++++++++++++---------
 10 files changed, 202 insertions(+), 52 deletions(-)
Signature · 1 line
1.7.10.4