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Unify interrupt register init/reset

Paulo Zanoni intel-gfx 1 version In review

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  1. v1 Latest15 patches 12 repliesIn review

Patches in v1 No applies recorded yet

#Subject and filesSizeRepliesApplied
1/15drm/i915: add INTEL_IRQ_REG_RESETdrivers/gpu/drm/i915/i915_irq.c+21 -370 replies
2/15drm/i915: change how VLV_IIR is resetdrivers/gpu/drm/i915/i915_irq.c+2 -40 replies
3/15drm/i915: port i965_irq_uninstall go INTEL_IRQ_REG_RESETdrivers/gpu/drm/i915/i915_irq.c+1 -33 replies
4/15drm/i915: really clear the IIR registersdrivers/gpu/drm/i915/i915_irq.c+8 -43 replies
5/15drm/i915: add INTEL_IRQ_REG_INITdrivers/gpu/drm/i915/i915_irq.c+14 -161 reply
6/15drm/i915: use INTEL_IRQ_REG_INIT on VLV toodrivers/gpu/drm/i915/i915_irq.c+1 -40 replies
7/15drm/i915: reset the IIR registers at preinstalldrivers/gpu/drm/i915/i915_irq.c+16 -191 reply
8/15drm/i915: WARN if IIR is not zero at irq_postinstalldrivers/gpu/drm/i915/i915_irq.c+1 -20 replies
9/15drm/i915: remove additional zerogin of VLV_IIR at postinstalldrivers/gpu/drm/i915/i915_irq.c+0 -30 replies
10/15drm/i915: remove extra clearing of GTIIR from VLV irq preinstalldrivers/gpu/drm/i915/i915_irq.c+0 -40 replies
11/15drm/i915: add INTEL_IRQ_REG_RESET16drivers/gpu/drm/i915/i915_irq.c+11 -61 reply
12/15drm/i915: really clear the IIR registers on i8xxdrivers/gpu/drm/i915/i915_irq.c+8 -40 replies
13/15drm/i915: add INTEL_IRQ_REG_INIT16drivers/gpu/drm/i915/i915_irq.c+14 -80 replies
14/15drm/i915: reset the i8xx IIR registers at preinstalldrivers/gpu/drm/i915/i915_irq.c+6 -90 replies
15/15drm/i915: WARN if IIR is not zero at i8xx irq_postinstalldrivers/gpu/drm/i915/i915_irq.c+2 -20 replies

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Cover letter [PATCH 00/15] Unify interrupt register init/reset

From: Paulo Zanoni <[email protected]>

Hi

This patch series is based on emails I sent a few days ago, with subject "proposals/questions about the IRQ registers". The biggest goal of the series is to have an unified way to initialize/reset IRQ regsiters. After this series, when you add new interrupts to our driver you won't need to think about doing the correct reads, writes and posting_reads, all you'll need to worry about is to call the macros everyone else calls. So now either all the registers are initialized correctly or all the registers are initialized wrongly.

The first 10 patches do all the rework on i915+. The changes should be incremental and any non-trivial changes are on separate patches, so bisecting regressions should be very easy. It is worth mentioning that patches 2, 6, 9 and 10 touch VLV-specific code, and I don't have a way to test this code.

On my intial patches the i8xx code was changed along with the i915+ code, but Ben suggested I shouldn't be touching i8xx code, so patches 11-15 do the i8xx work. I don't know if we really want these patches, but they're here anyway, so feel free to give them a NACK, I won't complain. In case we decide to merge the patches, git bisect should easily spot regressions.

Patches tested on Haswell (constant use for 2 weeks), SandyBridge (a few hours of usage) and Atom (only booted and then suspend/resumed once).

Thanks,
Paulo

Paulo Zanoni (15):
drm/i915: add INTEL_IRQ_REG_RESET
drm/i915: change how VLV_IIR is reset
drm/i915: port i965_irq_uninstall go INTEL_IRQ_REG_RESET drm/i915: really clear the IIR registers
drm/i915: add INTEL_IRQ_REG_INIT
drm/i915: use INTEL_IRQ_REG_INIT on VLV too
drm/i915: reset the IIR registers at preinstall drm/i915: WARN if IIR is not zero at irq_postinstall drm/i915: remove additional zerogin of VLV_IIR at postinstall drm/i915: remove extra clearing of GTIIR from VLV irq preinstall drm/i915: add INTEL_IRQ_REG_RESET16
drm/i915: really clear the IIR registers on i8xx drm/i915: add INTEL_IRQ_REG_INIT16
drm/i915: reset the i8xx IIR registers at preinstall drm/i915: WARN if IIR is not zero at i8xx irq_postinstall

 drivers/gpu/drm/i915/i915_irq.c | 144 +++++++++++++++++-----------------------
 1 file changed, 62 insertions(+), 82 deletions(-)
Signature · 1 line
1.8.1.2