target-ppc: VSX Bug Fixes
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- v2 Latest9 patches 7 repliesIn review
- v19 patches 5 repliesSuperseded
Patches in v2 No applies recorded yet
| # | Subject and files | Size | Replies | Applied |
|---|---|---|---|---|
| 1/9 | softfloat: Introduce float32_to_uint64_round_to_zerofpu/ include/ | +21 | 1 reply | |
| 2/9 | target-ppc: Bug: VSX Convert to Integer Should Truncatetarget-ppc/ | +2 | 0 replies | |
| 3/9 | target-ppc: Define Endian-Correct Accessors for VSR Field Acesstarget-ppc/ | +8 | 0 replies | |
| 4/9 | target-ppc: Correct LE Host Inversion of Lower VSRstarget-ppc/ | +4 | 0 replies | |
| 5/9 | target-ppc: Correct Simple VSR LE Host Inversionstarget-ppc/ | +190 | 0 replies | |
| 6/9 | target-ppc: Correct VSX Scalar Comparestarget-ppc/ | +7 | 0 replies | |
| 7/9 | target-ppc: Correct VSX FP to FP Conversionstarget-ppc/ | +4 | 0 replies | |
| 8/9 | target-ppc: Correct VSX FP to Integer Conversiontarget-ppc/ | +15 | 0 replies | |
| 9/9 | target-ppc: Correct VSX Integer to FP Conversiontarget-ppc/ | +13 | 0 replies |
Reviews trailers per patch
1 of 9 patches has a Reviewed-by or Acked-by.
| Patch | Tom Musta | Peter Maydell |
|---|---|---|
| 1/9 | T-b | R-b |
| 2/9 | T-b | |
| 3/9 | T-b | |
| 4/9 | T-b | |
| 5/9 | T-b | |
| 6/9 | T-b | |
| 7/9 | T-b | |
| 8/9 | T-b | |
| 9/9 | T-b |
Trailers given in replies are filled; those carried in the patches from earlier versions are outlined with dashes.
Cover letter [Qemu-devel] [V2 PATCH 0/9] target-ppc: VSX Bug Fixes
This patch series addresses bugs in the recently added VSX instructions. Two general defects are fixed:
(1) The VSX Convert to Integer instructions truncate the source floating point number to an integer value and hence should use a round-to-zero rounding algorithm. The existing implementation erroneously uses the rounding mode as set by the FPSCR.
This patch was previously published separately (see discussion at
http://lists.nongnu.org/archive/html/qemu-devel/2014-03/msg04526.html).
(2) There is a pervasive problem with the VSX helpers on Little Endian hosts. The bug can be seen when using a mixture of VSRs in the upper and lower regions of VSR (i.e. a mixture of VSR 0-31, which overlay the Floating Point register array, and VSR 32-64 which overlay the Altivec AVR array). This patch series introduces VSR field accessors that are consistent with the Power ISA notation irrespective of host endianness. The VSX instruction macros are updated to use these accessors.
For example, the Power ISA has pictures like this, describing a VSR:
0 32 64 96 127
+----------+----------+----------+----------+
| .word[0] | .word[1] | .word[2] | .word[3] |
+----------+----------+----------+----------+
The updated code will now refer to .word[0] as v->VsrW(0), .word[1] as v->VsrW(1), and so on.
This change makes the code correct and also more consistent with the ISA document.
V2: Simplified implementation of float32_to_uint64_round_to_zero per Peter Maydell's review.
Tom Musta (9):
softfloat: Introduce float32_to_uint64_round_to_zero
target-ppc: Bug: VSX Convert to Integer Should Truncate
target-ppc: Define Endian-Correct Accessors for VSR Field Acess
target-ppc: Correct LE Host Inversion of Lower VSRs
target-ppc: Correct Simple VSR LE Host Inversions
target-ppc: Correct VSX Scalar Compares
target-ppc: Correct VSX FP to FP Conversions
target-ppc: Correct VSX FP to Integer Conversion
target-ppc: Correct VSX Integer to FP Conversion
fpu/softfloat.c | 20 ++ include/fpu/softfloat.h | 1 + target-ppc/fpu_helper.c | 494 +++++++++++++++++++++++------------------------ 3 files changed, 264 insertions(+), 251 deletions(-)