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drm/i915/bdw: Implement a basic PM interrupt handler

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  1. v1 Latest10 patches 16 repliesIn review

Patches in v1 No applies recorded yet

#Subject and filesSizeRepliesApplied
1/10drm/i915/bdw: Implement a basic PM interrupt handlerdrivers/gpu/drm/i915/i915_irq.c drivers/gpu/drm/i915/i915_reg.h drivers/gpu/drm/i915/intel_drv.h +1 more+112 -41 reply
2/10drm/i915: Enable PM Interrupts target via Display Interface.drivers/gpu/drm/i915/i915_reg.h drivers/gpu/drm/i915/intel_pm.c+3 -01 reply
3/10drm/i915/chv: Enable Render Standby (RC6) for Cheeryviewdrivers/gpu/drm/i915/i915_reg.h drivers/gpu/drm/i915/intel_pm.c+99 -27 replies
4/10drm/i915/chv: Added CHV specific register read and writedrivers/gpu/drm/i915/intel_uncore.c+131 -82 replies
5/10drm/i915/chv: Enable RPS (Turbo) for Cheeryviewdrivers/gpu/drm/i915/i915_drv.h drivers/gpu/drm/i915/i915_reg.h drivers/gpu/drm/i915/intel_pm.c +1 more+107 -11 reply
6/10drm/i915/chv: Streamline CHV forcewake stuffdrivers/gpu/drm/i915/intel_uncore.c+32 -561 reply
7/10drm/i915/chv: CHV doesn't need WaRsForcewakeWaitTC0drivers/gpu/drm/i915/intel_uncore.c+2 -20 replies
8/10drm/i915/chv: Skip gen6_gt_check_fifodbg() on CHVdrivers/gpu/drm/i915/intel_uncore.c+4 -31 reply
9/10drm/i915/chv: Added CHV specific DDR fetch into init_clock_gatingdrivers/gpu/drm/i915/intel_pm.c+11 -01 reply
10/10drm/i915/chv: Freq(opcode) request value for CHV.drivers/gpu/drm/i915/i915_drv.h drivers/gpu/drm/i915/i915_irq.c+11 -21 reply

Reviews trailers per patch

All 10 patches have a Reviewed-by or Acked-by.

PatchMika KuoppalaBen Widawsky
1/10R-b
2/10R-b
3/10A-b
4/10R-b
5/10A-b
6/10R-b R-b
7/10R-b
8/10R-b R-b
9/10A-b
10/10R-b

Trailers given in replies are filled; those carried in the patches from earlier versions are outlined with dashes.

Read the v1 thread