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ARM/arm64 Barrier cleanups and fixes for 3.16

Will Deacon linux-arm-kernel 1 version New

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  1. v1 Latest8 patches 0 repliesNew

Patches in v1 No applies recorded yet

#Subject and filesSizeRepliesApplied
1/8ARM: cacheflush: use -st dsb option for ensuring completionarch/arm/include/asm/cacheflush.h arch/arm/mm/cache-v7.S arch/arm/mm/mmu.c+8 -80 replies
2/8ARM: cache: remove redundant dsb instruction from v7_coherent_user_rangearch/arm/mm/cache-v7.S+0 -11 reply
2/8ARM: cache: remove redundant dsb instruction from v7_coherent_user_range+0 -00 replies
3/8arm64: barriers: make use of barrier options with explicit barriersarch/arm64/include/asm/barrier.h arch/arm64/include/asm/cacheflush.h arch/arm64/include/asm/pgtable.h +3 more+15 -150 replies
4/8arm64: barriers: wire up new barrier optionsarch/arm64/include/asm/barrier.h+7 -70 replies
5/8arm64: barriers: use barrier() instead of smp_mb() when !SMParch/arm64/include/asm/barrier.h+2 -20 replies
6/8arm64: head: fix cache flushing and barriers in set_cpu_boot_mode_flagarch/arm64/kernel/head.S+3 -50 replies
7/8arm64: kvm: use inner-shareable barriers for inner-shareable maintenancearch/arm64/kvm/hyp.S+9 -30 replies
8/8arm64: mm: use inner-shareable barriers for inner-shareable maintenancearch/arm64/mm/cache.S arch/arm64/mm/proc.S arch/arm64/mm/tlb.S+8 -80 replies

Reviews trailers per patch

6 of 9 patches have a Reviewed-by or Acked-by.

PatchCatalin MarinasMarc Zyngier
1/8
2/8
2/8
3/8A-b
4/8A-b
5/8A-b
6/8A-b
7/8A-b A-b
8/8A-b

Trailers given in replies are filled; those carried in the patches from earlier versions are outlined with dashes.

Read the v1 thread

Cover letter [PATCH 0/8] ARM/arm64 Barrier cleanups and fixes for 3.16

Hello,

Here is the current set of barrier cleanups and fixes I plan to queue for merging in 3.16. Most of the arm64 patches have been posted before, but there are also a few additions that I wrote recently.

All feedback welcome,

Will

Will Deacon (8):
ARM: cacheflush: use -st dsb option for ensuring completion
ARM: cache: remove redundant dsb instruction from
v7_coherent_user_range
arm64: barriers: make use of barrier options with explicit barriers
arm64: barriers: wire up new barrier options
arm64: barriers: use barrier() instead of smp_mb() when !SMP
arm64: head: fix cache flushing and barriers in set_cpu_boot_mode_flag
arm64: kvm: use inner-shareable barriers for inner-shareable
maintenance
arm64: mm: use inner-shareable barriers for inner-shareable
maintenance

 arch/arm/include/asm/cacheflush.h   |  2 +-
 arch/arm/mm/cache-v7.S              | 13 ++++++-------
 arch/arm/mm/mmu.c                   |  2 +-
 arch/arm64/include/asm/barrier.h    | 20 ++++++++++----------
 arch/arm64/include/asm/cacheflush.h |  4 ++--
 arch/arm64/include/asm/pgtable.h    |  4 ++--
 arch/arm64/include/asm/tlbflush.h   | 14 +++++++-------
 arch/arm64/kernel/head.S            |  8 +++-----
 arch/arm64/kernel/process.c         |  2 +-
 arch/arm64/kvm/hyp.S                | 12 +++++++++---
 arch/arm64/kvm/sys_regs.c           |  4 ++--
 arch/arm64/mm/cache.S               |  6 +++---
 arch/arm64/mm/proc.S                |  2 +-
 arch/arm64/mm/tlb.S                 |  8 ++++----
 14 files changed, 52 insertions(+), 49 deletions(-)
Signature · 1 line
1.9.2