Skip to content

target-ppc: Assorted Floating Point Bugs and Cleanup

Tom Musta qemu-devel 2 versions – Applied

Status from this message: Thanks, applied with the following squashed in:

Get series with b4
b4 am [email protected]

Versions newest first · linked by author and title

  1. v2 Latest6 patches 4 repliesApplied
  2. v17 patches 6 repliesSuperseded

Patches in v2 Applied

#Subject and filesSizeRepliesApplied
1/6target-ppc: VXSQRT Should Not Be Set for NaNstarget-ppc/fpu_helper.c+17 -120 replies
2/6target-ppc: Fix Floating Point Move Instructions That Set CR1target-ppc/translate.c+30 -203 replies
3/6target-ppc: mffs. Should Set CR1 from FPSCR Bitstarget-ppc/translate.c+3 -10 replies
4/6target-ppc: Fully Migrate to gen_set_cr1_from_fpscrtarget-ppc/translate.c+33 -220 replies
5/6target-ppc: Eliminate set_fprf Argument From gen_compute_fprftarget-ppc/translate.c+23 -150 replies
6/6target-ppc: Eliminate set_fprf Argument From helper_compute_fprftarget-ppc/fpu_helper.c target-ppc/helper.h target-ppc/translate.c+28 -380 replies

Reviews trailers per patch

No Reviewed-by, Acked-by or Tested-by trailers for v2 yet.

Read the v2 thread

Cover letter [Qemu-devel] [2.3 V2 PATCH 0/6] target-ppc: Assorted Floating Point Bugs and Cleanup

This patch series corrects some issues with floating point emulation on Power.

Patch 1 corrects a corner case in the square root instructions, which incorrectly react to NaN whose sign bit is a 1.

Patches 2-6 correct a rather pervasive problem with modeling of the CR[1] field (i.e. the "dot form" instructions of the FPU).

The bugs were found by running random test patterns through actual Power hardware (P7 and P8) and comparing against QEMU.

The patches conflict quite a bit with Paolo's series that splits CR into 32 one bit registers. Paolo: is V3 of your patch series coming anytime soon?

V2 Reworked patches to pick up the gen_set_cr1_from_fpscr() utility that was recently added by Paolo Bonzini.

Tom Musta (6):
target-ppc: VXSQRT Should Not Be Set for NaNs
target-ppc: Fix Floating Point Move Instructions That Set CR1
target-ppc: mffs. Should Set CR1 from FPSCR Bits
target-ppc: Fully Migrate to gen_set_cr1_from_fpscr
target-ppc: Eliminate set_fprf Argument From gen_compute_fprf
target-ppc: Eliminate set_fprf Argument From helper_compute_fprf

 target-ppc/fpu_helper.c |   85 +++++++++++++++---------------
 target-ppc/helper.h     |    2 +-
 target-ppc/translate.c  |  131 ++++++++++++++++++++++++++++-------------------
 3 files changed, 122 insertions(+), 96 deletions(-)