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Enable high speed and heavy load for DDR4 for LSCH3

Joakim Tjernlund u-boot 1 version New

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  1. v1 Latest0 of 7 patches 0 repliesNew

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Cover letter [U-Boot] [PATCH v1 0/7] Enable high speed and heavy load for DDR4 for LSCH3
Quoted 6 lines · Yuantian Tang

Hi Jocke,

we achieved deep sleep mode that did exactly what you asked for.
If waken up from deep sleep, soc will resume from uboot and re-initialized DDR controller with contents untouched.
Please refer to drivers/ddr/fsl/fsl_ddr_gen4.c and look at DEEP_SLEEP related code.

Looking at it now and it looks the same as for ddr3? Some questions though:
289 if (is_warm_boot()) {

 289                 /* enter self-refresh */
 290                 temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg_2);
 291                 temp_sdram_cfg |= SDRAM_CFG2_FRC_SR;
 292                 ddr_out32(&ddr->sdram_cfg_2, temp_sdram_cfg);

Why do you need to force SR here? The DDR RAM must already be in SR at this point? I come from CPU reset state so my DDR controller has HW default values so this does not feel safe.

293 /* do board specific memory setup */
294 board_mem_sleep_setup();
295
296 temp_sdram_cfg = (ddr_in32(&ddr->sdram_cfg) | SDRAM_CFG_BI);
SDRAM_CFG_BI skips a lot(all?) init of DDR RAM. What if you want to change some DDR RAM timing/config due to a bug? Then you would have to force a cold start.

Do you use ECC? Seems to be some issues with ECC if you skip D_INIT

Jocke

Quoted 34 lines

Regards,
Yuantian

Quoted 30 lines

-----Original Message-----
From: Joakim Tjernlund [mailto:joakim.tjernlund at transmode.se]
Sent: Thursday, November 05, 2015 4:04 PM
To: Sun York-R58495 <[email protected]>; u-boot at lists.denx.de
Cc: curt at cumulusnetworks.com; Sharma Bhupesh-B45370 <[email protected]>; trini at konsulko.com; l.majewski at samsung.com; Tang Yuantian-B29983 <[email protected]>; Kushwaha Prabhakar-B32579 <[email protected]>; Liu Shengzhou-B36685 <[email protected]>; yamada.m at jp.panasonic.com
Subject: Re: [PATCH v1 0/7] Enable high speed and heavy load for DDR4 for LSCH3

Quoted 3 lines · York Sun

This patch set revises the DDR driver to support higher speed for DDR4 under heavy load (two dual-rank DIMMs) for four-chipselect interleaving. Single quad-rank DIMM is not supported yet.

Hi York

Seeing these patches reminds me about something I have been mening to ask, Is it possible init the ddr controller/ddr ram (using ECC also) but still retain (parts of) memory contents?

I am looking at keeping data at the end of memory when performing a warm start, but still init the controll/ddr ram (without D_INIT set). This way one could pick up any changes to DDR timing if needed. Before reboot, ddr ram is set to Self Refresh(SR).

Jocke

Read the cover letter in its thread