Enable high speed and heavy load for DDR4 for LSCH3

Quoted 38 lines

-----Original Message-----
From: York Sun [mailto:yorksun at freescale.com]
Sent: Friday, November 06, 2015 1:42 AM
To: Joakim Tjernlund <[email protected]>; Tang Yuantian- B29983 <[email protected]>; u-boot at lists.denx.de
Cc: Kushwaha Prabhakar-B32579 <[email protected]>; Sharma Bhupesh-B45370 <[email protected]>; trini at konsulko.com; Liu Shengzhou-B36685 <[email protected]>;
curt at cumulusnetworks.com; l.majewski at samsung.com; yamada.m at jp.panasonic.com
Subject: Re: [PATCH v1 0/7] Enable high speed and heavy load for DDR4 for LSCH3

Quoted 7 lines · Joakim Tjernlund

Quoted 6 lines · Yuantian Tang

Hi Jocke,

we achieved deep sleep mode that did exactly what you asked for. If waken up from deep sleep, soc will resume from uboot and re-initialized DDR controller with contents untouched. Please refer to drivers/ddr/fsl/fsl_ddr_gen4.c and look at DEEP_SLEEP

related code.

Quoted 9 lines

Looking at it now and it looks the same as for ddr3? Some questions though:
289 if (is_warm_boot()) {

 289                 /* enter self-refresh */
 290                 temp_sdram_cfg = ddr_in32(&ddr->sdram_cfg_2);
 291                 temp_sdram_cfg |= SDRAM_CFG2_FRC_SR;
 292                 ddr_out32(&ddr->sdram_cfg_2, temp_sdram_cfg);

Why do you need to force SR here? The DDR RAM must already be in SR at

this point?

Quoted 2 lines

I come from CPU reset state so my DDR controller has HW default values so this does not feel safe.

Quoted 4 lines

This may be redundant. If the code runs to this line, it should come back from a deep sleep. The core is in reset state but the DDR controller is not. It should be in self-refresh mode. I will leave that to Yuantian to comment.

This is mandatory. the steps are: re-enter SR mode, enable DDR controller, exit SR mode. We do that to smooth the transition and avoid any glitch caused when controller takes over memory.