target/xtensa: switch to libisa
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- v2 Latest16 patches 1 replyIn review
- v116 patches 3 repliesSuperseded
Changes in v2 from the cover letter
- add sed transformation to target/xtensa/import-core.sh that drops #include "ansidecl.h" from imported xtensa-modules.c;
- drop #include "ansidecl.h" from xtensa-modules.c for converted cores;
- reimplement translate_const16 using tcg_gen_deposit_i32.
Patches in v2 No applies recorded yet
| # | Subject and files | Size | Replies | Applied |
|---|---|---|---|---|
| 1/16 | target/xtensa: pass actual frame size to the entry helpertarget/ target/ | +2 | 0 replies | |
| 2/16 | target/xtensa: import libisa sourceinclude/ target/ target/ +2 more | +2816 | 0 replies | |
| 3/16 | target/xtensa: extract core opcode translatorstarget/ target/ | +3145 | 0 replies | |
| 4/16 | target/xtensa: extract FPU2000 opcode translatorstarget/ target/ | +375 | 0 replies | |
| 5/16 | target/xtensa: update import_core.sh script for libisatarget/ | +15 | 0 replies | |
| 6/16 | target/xtensa: switch dc232b to libisatarget/ target/ | +28 | 0 replies | |
| 7/16 | target/xtensa: switch dc233c to libisatarget/ target/ | +31 | 0 replies | |
| 8/16 | target/xtensa: switch fsf to libisatarget/ target/ | +29 | 0 replies | |
| 9/16 | target/xtensa: use libisa for instruction decodingtarget/ target/ target/ | +124 | 0 replies | |
| 10/16 | target/xtensa: tests: fix memctl SR testtests/ | +1 | 0 replies | |
| 11/16 | target/xtensa: drop DisasContext::litbasetarget/ | +5 | 0 replies | |
| 12/16 | target/xtensa: add internal/noop SRs and opcodestarget/ target/ | +35 | 0 replies | |
| 13/16 | target/xtensa: implement salt/saltutarget/ | +18 | 0 replies | |
| 14/16 | target/xtensa: implement GPIO32target/ target/ | +54 | 0 replies | |
| 15/16 | target/xtensa: implement const16target/ | +14 | 0 replies | |
| 16/16 | target/xtensa: implement disassemblerMAINTAINERS disas/ disas/ +2 more | +145 | 1 reply |
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Cover letter [Qemu-devel] [PATCH v2 00/16] target/xtensa: switch to libisa
Hello,
this series adds libisa to the Xtensa target, changes decoder and instruction translators to use it, switches existing xtensa cores to use it, adds support for a number of new instructions and adds disassembler for Xtensa.
Libisa is the canonical way of dealing with Xtensa instructions decoding and encoding. Libisa is a configuration-independent library with a stable interface plus generated configuration-specific xtensa-modules.c file with implementations of decoding and encoding functions. Libisa is MIT-licensed and originally distributed xtensa-modules.c files are also MIT-licensed and are available as a part of the xtensa configuration overlay.
This transition makes it possible to support variable-encoding instructions of the core ISA, like const16, and will allow to support advanced Xtensa features, like FLIX and TIE.
Development branch is available at:
git://github.com/OSLL/qemu-xtensa.git xtensa-libisa
Changes v1->v2:
- add sed transformation to target/xtensa/import-core.sh that drops #include "ansidecl.h" from imported xtensa-modules.c;
- drop #include "ansidecl.h" from xtensa-modules.c for converted cores;
- reimplement translate_const16 using tcg_gen_deposit_i32.
Max Filippov (16):
target/xtensa: pass actual frame size to the entry helper target/xtensa: import libisa source target/xtensa: extract core opcode translators target/xtensa: extract FPU2000 opcode translators target/xtensa: update import_core.sh script for libisa target/xtensa: switch dc232b to libisa target/xtensa: switch dc233c to libisa target/xtensa: switch fsf to libisa target/xtensa: use libisa for instruction decoding target/xtensa: tests: fix memctl SR test target/xtensa: drop DisasContext::litbase target/xtensa: add internal/noop SRs and opcodes target/xtensa: implement salt/saltu target/xtensa: implement GPIO32
target/xtensa: implement const16
target/xtensa: implement disassembler
MAINTAINERS | 1 + disas/Makefile.objs | 1 + disas/xtensa.c | 133 + include/disas/bfd.h | 1 + include/hw/xtensa/xtensa-isa.h | 838 ++ target/xtensa/Makefile.objs | 1 + target/xtensa/core-dc232b.c | 4 + target/xtensa/core-dc232b/xtensa-modules.c | 14105 +++++++++++++++++++++++++ target/xtensa/core-dc233c.c | 4 + target/xtensa/core-dc233c/xtensa-modules.c | 15232 +++++++++++++++++++++++++++ target/xtensa/core-fsf.c | 5 + target/xtensa/core-fsf/xtensa-modules.c | 9841 +++++++++++++++++ target/xtensa/cpu.c | 9 + target/xtensa/cpu.h | 31 + target/xtensa/helper.c | 37 + target/xtensa/import_core.sh | 15 + target/xtensa/op_helper.c | 2 +- target/xtensa/translate.c | 5883 +++++++---- target/xtensa/xtensa-isa-internal.h | 231 + target/xtensa/xtensa-isa.c | 1745 +++ target/xtensa/xtensa-isa.h | 1 + tests/tcg/xtensa/test_sr.S | 2 +- 22 files changed, 45949 insertions(+), 2173 deletions(-) create mode 100644 disas/xtensa.c create mode 100644 include/hw/xtensa/xtensa-isa.h create mode 100644 target/xtensa/core-dc232b/xtensa-modules.c create mode 100644 target/xtensa/core-dc233c/xtensa-modules.c create mode 100644 target/xtensa/core-fsf/xtensa-modules.c create mode 100644 target/xtensa/xtensa-isa-internal.h create mode 100644 target/xtensa/xtensa-isa.c create mode 100644 target/xtensa/xtensa-isa.h
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