Add generic set_rate clk_ops for PLL35xx and PLL36xx for samsung SoCs
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None of the 11 patches the cover letter announces are in this archive.
Reviews trailers per patch
| Patch | Mike Turquette |
|---|---|
| Series | A-b |
Trailers given in replies are filled; those carried in the patches from earlier versions are outlined with dashes.
Cover letter [PATCH v7 00/11] Add generic set_rate clk_ops for PLL35xx and PLL36xx for samsung SoCs
Quoted 8 lines · On Friday 21 of June 2013 10:18:01 Vikas Sajjan wrote:
Hi Mr. Kim,
On Thu, Jun 20, 2013 at 3:37 PM, Yadwinder Singh Brar
Quoted 3 lines · <[email protected]> wrote:
Hi Tomasz,
On Thu, Jun 20, 2013 at 3:30 PM, Tomasz Figa <[email protected]>
Quoted 23 lines · wrote:
Quoted 23 lines
Quoted 23 lines
Hi Yadwinder, Vikas,
Quoted 19 lines · On Tuesday 11 of June 2013 15:01:05 Yadwinder Singh Brar wrote:
This patch series does the following:
1) Unifies the clk strutures and registration function used for PLL35xx>>>
& PLL36xx, to factor out possible common code.2) Defines a common
rate_tablewhich will contain recommended p, m, sand k values for supported rates that needs to be changed for changing
corresponding PLL's rate3) Adds
set_rate()andround_rate()clk_opsfor PLL35xx and PLL36xxchanges since v6:
- Splited the patch addingsamsung_clk_register_pll()into definition
addition, SoC specific migration and cleanup patches.
- Addressed some NIT comments.
Quoted 6 lines
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This version looks good to me. Thanks for your work on improving this series again!
Reviewed-by Tomasz Figa <[email protected]>Can you apply this series..
I think we need at least Mike's (clk subsystem maintainer) ACK here.
Mike, do you have any objections?
Best regards,
Tomasz
Quoted 121 lines
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Thanks for helping to improve this series.
Thanks,
YadwinderQuoted 97 lines
Best regards,
TomaszQuoted 22 lines
changes since v5:
- Corrected to use rate table as specified in UM for exynos5250 epll.
- Took care of exynos5420 as well, as new exynos5420 clk driver came in
while rebasing on latest Kgene's for-next.Since we spilted 1st patch into 2 different patches, can we expect "reviewed-by" again for the same?
changes since v4:
- Defined common samsungsamsung_clk_register_pll()to register a list
of PLL and used a structsamsung_pll_clockfor passing intialisation
data instead of passing as arguments. Now passing LOCK as well as CON0
offset as intialisation data.
- Calculated length of rate table while registering PLL instead of
getting it as intialisation data.Quoted 9 lines
changes since v3:
- Used__clk_lookup()instead of adding alias formout_vpllsrc
- Added check for changing only M value insamsung_pll36xx_set_rate()
- Modifiedsamsung_pll35xx_mp_change()&samsung_pll35xx_set_rate()
to improve readabilty.
- Made the inputrate_tableas__init_datawhich is to be providedwhile
Quoted 60 lines
registering PLL and made a copy of that table while registering, so that if multiple tables are their, they can be freed after getting the P, M, S, K setting values from required one.
changes since v2:
- Added new patch to reorder the MUX registration formout_vpllsrcMUX
before the PLL registrations. And to add the alias for themout_vpllsrcMUX. - Added a check to confirm parent rate while registrating the PLL
rate tables.changes since v1:
- removed sorting and bsearch
- modified the definition of struct "samsung_pll_rate_table"
- added genericround_rate()
- rectified the ops assignment for "rate table passed as NULLIs rebased on branch kgene's "for-next"
https://git.kernel.org/cgit/linux/kernel/git/kgene/linux-samsung.git
/log/ ?h=for-nextVikas Sajjan (3):
clk: samsung: Addset_rate()clk_opsfor PLL36xx
clk: samsung: Reorder MUX registration formout_vpllsrc
clk: samsung: Add EPLL and VPLL freq table for exynos5250 SoCYadwinder Singh Brar (8):
clk: samsung: Introduce a commonsamsung_clk_pllstruct
clk: samsung: Define a commonsamsung_clk_register_pll()
clk: samsung: Migrate exynos5250 to use common
samsung_clk_register_pll()clk: samsung: Migrate exynos4 to use common
samsung_clk_register_pll()clk: samsung: Migrate exynos5420 to use common
samsung_clk_register_pll()clk: samsung: Remove unused pll registeration code for pll35xx and
pll36xxclk: samsung: Add support to register
rate_tablefor samsung plls
clk: samsung: Addset_rate()clk_opsfor PLL35xxdrivers/clk/samsung/clk-exynos4.c | 40 +++-- drivers/clk/samsung/clk-exynos5250.c | 101 +++++++++-- drivers/clk/samsung/clk-exynos5420.c | 86 ++++++--- drivers/clk/samsung/clk-pll.c | 339++++++++++++++++++++++++++--------
drivers/clk/samsung/clk-pll.h| 38 ++++-
Quoted 8 lines
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drivers/clk/samsung/clk.h | 53 ++++++ 6 files changed, 519 insertions(+), 138 deletions(-)--
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