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riscv: Adding RISC-V CPU and timer driver

Bin Meng u-boot 1 version New

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  1. v1 Latest19 patches 0 repliesNew

Patches in v1 No applies recorded yet

#Subject and filesSizeRepliesApplied
1/19riscv: add Kconfig entries for the code modelarch/riscv/Kconfig arch/riscv/Makefile+26 -10 replies
2/19dm: cpu: Add timebase frequency to the platdatainclude/cpu.h+3 -02 replies
2/19dm: cpu: Add timebase frequency to the platdata+0 -01 reply
3/19riscv: qemu: Create a simple-bus driver for the soc nodearch/riscv/cpu/qemu/cpu.c+13 -01 reply
3/19riscv: qemu: Create a simple-bus driver for the soc node+0 -00 replies
4/19cpu: Add a RISC-V CPU driverdrivers/cpu/Kconfig drivers/cpu/Makefile drivers/cpu/riscv_cpu.c+124 -01 reply
4/19cpu: Add a RISC-V CPU driver+0 -01 reply
5/19riscv: Add a SYSCON driver for Core Local Interruptorarch/riscv/Kconfig arch/riscv/include/asm/clint.h arch/riscv/lib/Makefile +1 more+102 -02 replies
5/19riscv: Add a SYSCON driver for Core Local Interruptor+0 -02 replies
5/19riscv: Add a SYSCON driver for Core Local Interruptor+0 -01 reply
5/19riscv: Add a SYSCON driver for Core Local Interruptor+0 -01 reply
5/19riscv: Add a SYSCON driver for Core Local Interruptor+0 -00 replies
5/19riscv: Add a SYSCON driver for Core Local Interruptor+0 -00 replies
6/19timer: Add driver for RISC-V privileged architecture defined timerdrivers/timer/Kconfig drivers/timer/Makefile drivers/timer/riscv_timer.c+59 -00 replies
7/19riscv: kconfig: Allow platform to specify Kconfig optionsarch/riscv/Kconfig arch/riscv/cpu/qemu/Kconfig board/emulation/qemu-riscv/Kconfig+16 -01 reply
8/19riscv: Enlarge the default SYS_MALLOC_F_LENarch/riscv/Kconfig+3 -01 reply
9/19riscv: qemu: Probe cpus during bootarch/riscv/cpu/qemu/Kconfig arch/riscv/cpu/qemu/cpu.c+15 -01 reply
9/19riscv: qemu: Probe cpus during boot+0 -00 replies
10/19riscv: Add CSR numbersarch/riscv/include/asm/encoding.h+219 -01 reply
10/19riscv: Add CSR numbers+0 -00 replies
11/19riscv: Add exception codes for xcause registerarch/riscv/include/asm/encoding.h+15 -00 replies
12/19riscv: Do some basic architecture level cpu initializationarch/riscv/cpu/cpu.c+21 -01 reply
12/19riscv: Do some basic architecture level cpu initialization+0 -01 reply
13/19riscv: Move trap handler codes to mtrap.Sarch/riscv/cpu/Makefile arch/riscv/cpu/mtrap.S arch/riscv/cpu/start.S+107 -831 reply
14/19riscv: Fix context restore before returning from trap handlerarch/riscv/cpu/mtrap.S+1 -11 reply
15/19riscv: Return to previous privilege level after trap handlingarch/riscv/cpu/mtrap.S+0 -31 reply
16/19riscv: Adjust the _exit_trap() position to come before handle_trap()arch/riscv/lib/interrupts.c+30 -321 reply
17/19riscv: Pass correct exception code to _exit_trap()arch/riscv/lib/interrupts.c+1 -11 reply
17/19riscv: Pass correct exception code to _exit_trap()+0 -01 reply
18/19riscv: Refactor handle_trap() a little for future extensionarch/riscv/lib/interrupts.c+10 -61 reply
19/19riscv: Allow U-Boot to run on hart 0 onlyarch/riscv/cpu/start.S+4 -01 reply

Reviews trailers per patch

14 of 31 patches have a Reviewed-by or Acked-by.

PatchSimon GlassLukas Auer
1/19
2/19R-b R-b
2/19R-b R-b
3/19R-b
3/19R-b
4/19
4/19
5/19
5/19
5/19
5/19
5/19
5/19
6/19
7/19R-b
8/19R-b
9/19R-b
9/19R-b
10/19
10/19
11/19
12/19
12/19
13/19R-b
14/19R-b
15/19R-b
16/19R-b
17/19
17/19
18/19R-b
19/19R-b

Trailers given in replies are filled; those carried in the patches from earlier versions are outlined with dashes.

Read the v1 thread

Cover letter [U-Boot] [PATCH 00/19] riscv: Adding RISC-V CPU and timer driver

This adds DM drivers to support RISC-V CPU and timer.

The U-Boot RISC-V SBI support is still working in progress. Some patches in this series like adding CSR numbers, exception numbers, are prerequisites for the SBI implementation, but it does no harm to include them as part of this series.

This series is dependent on Lukas's riscv series @
http://patchwork.ozlabs.org/project/uboot/list/?series=74999

This series is available at u-boot-x86/riscv-working for testing.

Bin Meng (18):
dm: cpu: Add timebase frequency to the platdata
riscv: qemu: Create a simple-bus driver for the soc node
cpu: Add a RISC-V CPU driver
riscv: Add a SYSCON driver for Core Local Interruptor
timer: Add driver for RISC-V privileged architecture defined timer
riscv: kconfig: Allow platform to specify Kconfig options
riscv: Enlarge the default SYS_MALLOC_F_LEN
riscv: qemu: Probe cpus during boot
riscv: Add CSR numbers
riscv: Add exception codes for xcause register
riscv: Do some basic architecture level cpu initialization
riscv: Move trap handler codes to mtrap.S
riscv: Fix context restore before returning from trap handler
riscv: Return to previous privilege level after trap handling
riscv: Adjust the _exit_trap() position to come before handle_trap()
riscv: Pass correct exception code to _exit_trap()
riscv: Refactor handle_trap() a little for future extension
riscv: Allow U-Boot to run on hart 0 only

Lukas Auer (1):
riscv: add Kconfig entries for the code model

 arch/riscv/Kconfig                 |  35 ++++++
 arch/riscv/Makefile                |   9 +-
 arch/riscv/cpu/Makefile            |   2 +-
 arch/riscv/cpu/cpu.c               |  21 ++++
 arch/riscv/cpu/mtrap.S             | 103 ++++++++++++++++
 arch/riscv/cpu/qemu/Kconfig        |  10 ++
 arch/riscv/cpu/qemu/cpu.c          |  27 +++++
 arch/riscv/cpu/start.S             |  86 +-------------
 arch/riscv/include/asm/clint.h     |  24 ++++
 arch/riscv/include/asm/encoding.h  | 234 +++++++++++++++++++++++++++++++++++++
 arch/riscv/lib/Makefile            |   1 +
 arch/riscv/lib/clint.c             |  69 +++++++++++
 arch/riscv/lib/interrupts.c        |  78 +++++++------
 board/emulation/qemu-riscv/Kconfig |   1 +
 drivers/cpu/Kconfig                |   6 +
 drivers/cpu/Makefile               |   1 +
 drivers/cpu/riscv_cpu.c            | 117 +++++++++++++++++++
 drivers/timer/Kconfig              |   8 ++
 drivers/timer/Makefile             |   1 +
 drivers/timer/riscv_timer.c        |  50 ++++++++
 include/cpu.h                      |   3 +
 21 files changed, 764 insertions(+), 122 deletions(-)
 create mode 100644 arch/riscv/cpu/mtrap.S
 create mode 100644 arch/riscv/cpu/qemu/Kconfig
 create mode 100644 arch/riscv/include/asm/clint.h
 create mode 100644 arch/riscv/lib/clint.c
 create mode 100644 drivers/cpu/riscv_cpu.c
 create mode 100644 drivers/timer/riscv_timer.c
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