Skip to content

dcache support for Raspberry Pi 1

Alexander Stein u-boot 1 version New

Get series with b4
b4 am 1635379.iokOHN4OQt@kongar

Versions newest first

  1. v1 Latest0 of 5 patches 0 repliesNew

Patches in v1 No applies recorded yet

None of the 5 patches the cover letter announces are in this archive.

Reviews trailers per patch

No Reviewed-by, Acked-by or Tested-by trailers for v1 yet.

Read the v1 thread

Cover letter [U-Boot] [PATCH 0/5] dcache support for Raspberry Pi 1

Hello Albert,

On Monday 06 July 2015, 09:39:40 wrote Albert ARIBAUD:

Quoted 9 lines
Quoted 3 lines · Alexander Stein

dcache supprt increases the MMC read performance on RPI 1 from 5,4 MiB/s to 12.3 MiB/s. It doesn't seem to have any affect on RPI 2 though. I just get error messages about non-cacheline aligned address upon invalidation.

Could it be that code needed to support dcache is not the same for rpi_2's bcm2836 than it is for rpi's bcm2835?

Sure, bcm2835 is a armv6 while bcm2836 is a armv7.

Quoted 3 lines

Anyway: if code properly handles unaligned addresses then it should not throw an error message about it. Can you look into why the error is thrown?

Apparently it does not handle non-cacheline aligned addresses transparently or silently.

Here is the part of the code:

Quoted 12 lines

static void v7_dcache_inval_range(u32 start, u32 stop, u32 line_len)

{
	/*
	 * If start address is not aligned to cache-line do not
	 * invalidate the first cache-line
	 */
	if (start & (line_len - 1)) {
		printf("ERROR: %s - start address is not aligned - 0x%08x\n",
			__func__, start);
		/* move to next cache line */
		start = (start + line_len - 1) & ~(line_len - 1);
	}

I don't know why (a) the cache invalidation is only done from the next cache line and (b) why this can't be done transparently without printing an error. But currently I'm not keen on fiddling with armv7 caches.

Best regards,
Alexander

Read the cover letter in its thread