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2.6.22-rc3 perfmon2 : IBS implementation for AMD64

Robert Richter lkml 1 version Applied

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  1. v1 Latest8 patches 10 repliesApplied

Patches in v1 Applied

#Subject and filesSizeRepliesApplied
1/82.6.22-rc3 perfmon2 : IBS implementation for AMD64arch/i386/perfmon/perfmon.c arch/x86_64/perfmon/perfmon_k8.c+7 -13 replies
2/82.6.22-rc3 perfmon2 : IBS implementation for AMD64include/asm-i386/perfmon.h perfmon/perfmon.c perfmon/perfmon_file.c +3 more+69 -51 reply
3/82.6.22-rc3 perfmon2 : IBS implementation for AMD64arch/x86_64/perfmon/perfmon_k8.c include/asm-i386/perfmon.h include/linux/perfmon_pmu.h+29 -291 reply
4/82.6.22-rc3 perfmon2 : IBS implementation for AMD64include/asm-i386/msr-index.h+12 -103 replies
5/82.6.22-rc3 perfmon2 : IBS implementation for AMD64arch/i386/perfmon/perfmon.c arch/x86_64/perfmon/perfmon_k8.c include/asm-i386/msr-index.h +1 more+29 -110 replies
6/82.6.22-rc3 perfmon2 : IBS implementation for AMD64arch/i386/perfmon/perfmon.c arch/x86_64/perfmon/perfmon_k8.c include/asm-i386/msr-index.h +3 more+409 -212 replies
7/82.6.22-rc3 perfmon2 : IBS implementation for AMD64arch/x86_64/perfmon/perfmon_k8.c+45 -450 replies
8/82.6.22-rc3 perfmon2 : IBS implementation for AMD64arch/i386/perfmon/Kconfig arch/i386/perfmon/Makefile arch/i386/perfmon/perfmon.c +4 more+492 -4910 replies

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Cover letter [patch 0/8] 2.6.22-rc3 perfmon2 : IBS implementation for AMD64

Hello,

the following series of patches adds support for Instruction Based Sampling (IBS) of Barcelona CPUs. IBS is a code profiling mechanism that enables the processor to select a random instruction fetch or micro-op after a programmed time interval has expired and record specific performance information about the operation.

The patches also include a new AMD64 PMU description that dynamically detects the availability of PMU features of the CPU during configuration. Thus, there is only one description needed for all AMD CPU families and models (includes K8, families 10h and above).

The patches are relative to Stephane's 22 patches for 2.6.22-rc3.

Regards,
Robert

--
AMD Saxony, Dresden, Germany
Operating System Research Center
email: [email protected]