x86: Reduce Memory Usage and Inter-Node message traffic (v2)
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- v1 Latest6 patches 11 repliesIn review
Patches in v1 No applies recorded yet
| # | Subject and files | Size | Replies | Applied |
|---|---|---|---|---|
| 1/6 | x86: fix cpu_to_node references (v2)arch/ arch/ arch/ | +5 | 2 replies | |
| 2/6 | x86: Convert cpu_core_map to be a per cpu variable (v2)arch/ arch/ arch/ +9 more | +64 | 0 replies | |
| 3/6 | x86: Convert cpu_sibling_map to be a per cpu variable (v2)arch/ arch/ arch/ +10 more | +50 | 5 replies | |
| 4/6 | x86: Convert x86_cpu_to_apicid to be a per cpu variable (v2)arch/ arch/ arch/ +9 more | +80 | 0 replies | |
| 5/6 | x86: Convert cpu_llc_id to be a per cpu variable (v2)arch/ arch/ arch/ +2 more | +17 | 0 replies | |
| 6/6 | x86: acpi-use-cpu_physical_id (v2)arch/ drivers/ | +3 | 0 replies |
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Cover letter [PATCH 0/6] x86: Reduce Memory Usage and Inter-Node message traffic (v2)
Changes for version v2:
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Note the addtional change of the
cpu_llc_idtype from u8 to int for ARCHx86_64to correspond with ARCH i386.At least currently it cannot be more than 8 bit. So why waste memory? It would be better to change i386
Done. (x86_64 type => u8).
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Fix four instances where
cpu_to_nodeis referencedQuoted 2 lines
by array instead of via the
cpu_to_nodemacro. This is preparation to moving it to theper_cpudata area.Shouldn't this patch be logically before the per cpu conversion (which is 3/6). This way the result would be git bisectable.
Done. (Moved to PATCH 1/6).
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processor_core.ccurrently tries to determine the apicid by special casing for IA64 and x86. The desired information is readily available via
cpu_physical_id()on IA64, i386 and
x86_64.Have you tried this with a !CONFIG_SMP build? The
drivers/dmacode was doing the same and running into problems because it wasn't defined there.
Fixed. (New export in PATCH 6/6).
Previous Intro:
In x86_64 and i386 architectures most arrays that are sized using NR_CPUS lay in local memory on node 0. Not only will most (99%?) of the systems not use all the slots in these arrays, particularly when NR_CPUS is increased to accommodate future very high cpu count systems, but a number of cache lines are passed unnecessarily on the system bus when these arrays are referenced by cpus on other nodes.
Typically, the values in these arrays are referenced by the cpu accessing it's own values, though when passing IPI interrupts, the cpu does access the data relevant to the targeted cpu/node. Of course, if the referencing cpu is not on node 0, then the reference will still require cross node exchanges of cache lines. A common use of this is for an interrupt service routine to pass the interrupt to other cpus local to that node.
Ideally, all the elements in these arrays should be moved to the per_cpu data area. In some cases (such as x86_cpu_to_apicid) the array is referenced before the per_cpu data areas are setup. In this case, a static array is declared in the __initdata area and initialized by the booting cpu (BSP). The values are then moved to the per_cpu area after it is initialized and the original static array is freed with the rest of the __initdata.
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