OMAP2/3 clock: revise DPLL bypass handling in clock tree
Get series with b4
b4 am [email protected]Versions newest first · linked by author and title
- v2 Latest7 patches 0 repliesNew
- v16 patches 0 repliesSuperseded
Patches in v2 No applies recorded yet
| # | Subject and files | Size | Replies | Applied |
|---|---|---|---|---|
| 1/7 | OMAP3 clock: convert dpll_data.idlest_bit to idlest_maskarch/ arch/ arch/ | +8 | 0 replies | |
| 2/7 | OMAP3 clock: add idlest_reg, idlest_mask for DPLL3arch/ | +2 | 0 replies | |
| 3/7 | OMAP3 clock: note the bypass source clock for DPLLsarch/ arch/ | +10 | 0 replies | |
| 4/7 | OMAP3 clock: move DPLL bypass rate calculation into omap2_get_dpll_rate()arch/ arch/ arch/ +1 more | +58 | 0 replies | |
| 5/7 | OMAP3 clock: omap3_clkoutx2_recalc() should test DPLL IDLEST to determine if DPLL is bypassedarch/ | +3 | 0 replies | |
| 6/7 | OMAP3 clock: DPLLs should enter bypass if new rate is sys_ckarch/ | +29 | 0 replies | |
| 7/7 | OMAP3 clock: recalculate DPLL subtree after bypass entry/exitarch/ | +15 | 0 replies |
Reviews trailers per patch
No Reviewed-by, Acked-by or Tested-by trailers for v2 yet.
Cover letter [PATCH v2 0/7] OMAP2/3 clock: revise DPLL bypass handling in clock tree
This second version fixes bypass handling for DPLL1 and DPLL2 to use the high-frequency bypass clocks. This came to light courtesy of Kevin Hilman <[email protected]>.
---
Previously, the OMAP3 clock tree handled DPLL bypass rate recalculation by dynamically switching clock parents depending on the DPLL bypass state. It used the clksel mechanism for this. Unfortunately, this does not actually work. The clock code expects the clock's parent to be the one set in the struct clk, causing kernel messages similar to:
clock: Could not find fieldval 0 for clock iva2_ck parent dpll2_m2_ck
This patch series moves DPLL bypass rate computation into omap2_get_dpll_rate(), and removes most of the bypass clocks in the clock tree. It also converts the bypass tests in the code to use the DPLL IDLEST bits rather than the DPLL CLKEN bits.
Problem reported by Ramesh Gupta Guntha <[email protected]>.
Bypass rate recalculation verified with DPLL1 on 3430SDP, which has bypass support built into its clock code. Boot-tested on 2430SDP.
- Paul
---
text data bss dec hex filename
3443780 158320 105504 3707604 3892d4 vmlinux.3430sdp.orig 3443344 158160 105504 3707008 389080 vmlinux.3430sdp
arch/arm/mach-omap2/clock.c | 45 ++++++- arch/arm/mach-omap2/clock24xx.c | 4 - arch/arm/mach-omap2/clock24xx.h | 2 arch/arm/mach-omap2/clock34xx.c | 70 ++++++++---- arch/arm/mach-omap2/clock34xx.h | 188 +++++-------------------------- arch/arm/plat-omap/include/mach/clock.h | 5 - 6 files changed, 125 insertions(+), 189 deletions(-)