VMX EPT misconfigurtion handler
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- v1 Latest5 patches 13 repliesIn review
Patches in v1 No applies recorded yet
| # | Subject and files | Size | Replies | Applied |
|---|---|---|---|---|
| 1/5 | KVM: VMX: more MSR_IA32_VMX_EPT_VPID_CAP capability bitsarch/ arch/ | +27 | 0 replies | |
| 1/5 | KVM: VMX: more MSR_IA32_VMX_EPT_VPID_CAP capability bitsarch/ arch/ | +27 | 0 replies | |
| 1/5 | KVM: VMX: more MSR_IA32_VMX_EPT_VPID_CAP capability bitsarch/ arch/ | +27 | 0 replies | |
| 2/5 | KVM: MMU: make for_each_shadow_entry aware of largepagesarch/ | +5 | 4 replies | |
| 2/5 | KVM: MMU: make for_each_shadow_entry aware of largepagesarch/ | +5 | 0 replies | |
| 2/5 | KVM: MMU: make for_each_shadow_entry aware of largepagesarch/ | +5 | 0 replies | |
| 3/5 | KVM: MMU: add kvm_mmu_shadow_walk helperarch/ arch/ | +28 | 7 replies | |
| 3/5 | KVM: MMU: add kvm_mmu_get_spte_hierarchy helperarch/ arch/ | +20 | 3 replies | |
| 3/5 | KVM: MMU: add kvm_mmu_get_spte_hierarchy helperarch/ arch/ | +20 | 0 replies | |
| 4/5 | KVM: VMX: EPT misconfiguration handlerarch/ | +96 | 0 replies | |
| 4/5 | KVM: VMX: EPT misconfiguration handlerarch/ | +86 | 0 replies | |
| 4/5 | KVM: VMX: EPT misconfiguration handlerarch/ | +85 | 0 replies | |
| 5/5 | KVM: VMX: conditionally disable 2M pagesarch/ include/ virt/ | +16 | 1 reply | |
| 5/5 | KVM: VMX: conditionally disable 2M pagesarch/ include/ virt/ | +16 | 0 replies | |
| 5/5 | KVM: VMX: conditionally disable 2M pagesarch/ include/ virt/ | +16 | 0 replies |
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No Reviewed-by, Acked-by or Tested-by trailers for v1 yet.
Cover letter [patch 0/5] VMX EPT misconfigurtion handler
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From the Intel docs:
An EPT misconfiguration occurs when, in the course of translation a guest-physical address, the logical processor encounters an EPT paging-structure entry that contains an unsupported value.
Handle this event and print useful information for diagnostics.