ARM: Disable outer cache before kexec call
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Cover letter [patch 0/2] ARM: Disable outer cache before kexec call
Quoted 18 lines · Thomas Gleixner
Catalin,
Quoted 14 lines · Catalin Marinas
Quoted 12 lines · Thomas Gleixner
Quoted 9 lines · Catalin Marinas
Quoted 4 lines · Thomas Gleixner
The following patch series addresses the problem, that the kexec code does not disable the outer cache before disabling the inner cache and jumping into the new kernel. This results in random crashes of the new kernel.
We may need other ways to work around this problem. There are platforms like OMAP3 (I think) where the L2 cache cannot be disabled as Linux is running in non-secure (normal) mode.
But it can disable the inner caches? That's weird.
Quoted 7 lines
Quoted 5 lines
That's because the CP15 SCTLR register is a banked one, so independent configuration for secure and normal worlds.
The outer cache controller doesn't have banked registers and I'm not even sure it has a notion of secure or non-secure cache line.
Brilliant design.
FYI, on secure omaps disabling/enabling/configuring of L2 cache must be done via SMI that runs some function in the secure software (PPA).. The code is there in arch/arm/mach-omap2/sleep34xx.S, just search for SMI or PPA.
Trying to set things via the ARM aux ctrl register will hang the system, so we need to figure out some way to select the L2 enable/disable based on if we're running in secure mode or not.
Regards,
Tony