ARM: Disable outer cache before kexec call -V3
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b4 am [email protected]Versions newest first
- v1 Latest2 patches 0 repliesNew
Patches in v1 No applies recorded yet
| # | Subject and files | Size | Replies | Applied |
|---|---|---|---|---|
| 1/2 | arm: Disable outer (L2) cache in kexec | +0 | 1 reply | |
| 2/2 | arm: Implement l2x0 cache disable functions | +0 | 2 replies |
Reviews trailers per patch
All 2 patches have a Reviewed-by or Acked-by.
| Patch | Catalin Marinas |
|---|---|
| 1/2 | A-b |
| 2/2 | A-b |
Trailers given in replies are filled; those carried in the patches from earlier versions are outlined with dashes.
Cover letter [patch 0/2] ARM: Disable outer cache before kexec call -V3
The following patch series addresses the problem that the kexec code does not disable the outer cache before disabling the inner cache and jumping into the new kernel. This results in random crashes of the new kernel.
Changes since version 2:
- Use CLEAN_INV_WAY in l2x0_flush_all according to Catalin
- Rename outer_cache_disable() to outer_disable()
- Added a BUG_ON() when l2x0_inv_all() is called with L2 enabled.
Thanks,
tglx