Skip to content

Cmpxchg and xchg operations

Christoph Lameter linux-acpi lkml 2 versions – In review

Get series with b4
b4 am [email protected]

Versions newest first · linked by author and title

  1. v2 Latest5 patches 43 repliesIn review
  2. v14 patches 6 repliesSuperseded

Changes in v2 from the cover letter

- Determine that cmpxchg without LOCK is faster than xchg with implied lock (numbers are in the patch description).
- Drop 64 bit cpuops operations on 32 bit x86 (resulted in various nasty things such as 64 bit alignment requirements for 64 bit entities on 32 bit, sizable inline code and very complex macros)

Patches in v2 No applies recorded yet

#Subject and filesSizeRepliesApplied
1/5percpu: Generic this_cpu_cmpxchg() and this_cpu_xchg supportinclude/linux/percpu.h+135 -71 reply
2/5x86: this_cpu_cmpxchg and this_cpu_xchg operationsarch/x86/Kconfig.cpu arch/x86/include/asm/percpu.h+111 -11 reply
3/5irq_work: Use per cpu atomics instead of regular atomicskernel/irq_work.c+9 -98 replies
4/5vmstat: User per cpu atomics to avoid interrupt disable / enablemm/vmstat.c+87 -142 replies
5/5cpuops: Use cmpxchg for xchg to avoid lock semanticsarch/x86/include/asm/percpu.h+15 -631 replies

Reviews trailers per patch

2 of 5 patches have a Reviewed-by or Acked-by.

PatchMathieu DesnoyersH. Peter AnvinTejun Heo
1/5
2/5
3/5A-b
4/5
5/5A-b A-b A-b A-b A-b A-b

Trailers given in replies are filled; those carried in the patches from earlier versions are outlined with dashes. Scroll the table sideways for all 3 reviewers.

Read the v2 thread

Cover letter [cpuops cmpxchg V2 0/5] Cmpxchg and xchg operations

Add cmpxchg and xchg operations to the cpu ops and use them for irq handling and for vm statistics.

Requires the per cpu patches for and_return cpu ops.

V1->V2:
- Determine that cmpxchg without LOCK is faster than xchg with implied lock (numbers are in the patch description).
- Drop 64 bit cpuops operations on 32 bit x86 (resulted in various nasty things such as 64 bit alignment requirements for 64 bit entities on 32 bit, sizable inline code and very complex macros)