perf_events: update extra shared registers management (v4)

The following short series of patches improves the code which manages the extra shared regs used by some events on Intel processors. Those events require an extra MSR which may be shared between siblings CPUs when HT is on. When HT is off, the kernel still needs to ensure that events within an event group do not try to program different values into that extra MSR.

This series improves the current code for managing the register sharing by using static allocation instead of dynamically trying to find a table slot to host that extra MSR. This greatly simplifies the code. The patch also prepare the kernel for more registers with those kinds of constraints (e.g, LBR_SELECT, LD_LAT).

The patch also adds the missing group validation of events using those extra MSRs. Up until now, one could put two instances of the those events which had incompatible values for the extra MSR. There was no upfront check and the group would never be scheduled. Now, such group cannot be constructed anymore (fail early).

Finally, the third patch adds the SandyBridge support for the offcore_response events (which use these shared MSR). It also removes the offcore_response events from the SandyBridge constraint event table. Those events don't have any constraints contrary to what's published in the documentation.

The second version updates PATCH 1/3 which was an older version with reg->idx initialization problems.

The third version solves the lockdep issues by using spin_lock_irqsave in __intel_shared_reg_get_constraints().

The fourth version solves a compilation issue with patch 2/3 when Intel processor support is disabled. Patch 3/3 also includes a change in flags suggested by Peter Zijlstra.

[PATCH 0/3] introduction
[PATCH 1/3] rework of the register sharing logic [PATCH 2/3] add missing shared regs validation [PATCH 3/3] add Intel SandyBridge offcore_response support

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