USB and cache related fixes
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b4 am [email protected]Versions newest first
- v1 Latest2 of 4 patches 0 repliesNew
2 of 4 patches are in this archive. The cover letter announces 4.
Patches in v1 No applies recorded yet
| # | Subject and files | Size | Replies | Applied |
|---|---|---|---|---|
| 2/4 | cache_v7: Check for dcache enablement in dcache flush functions | +0 | 1 reply | |
| 2/4 | cache_v7: Check for dcache enablement in dcache flush functions | +0 | 0 replies |
Reviews trailers per patch
No Reviewed-by, Acked-by or Tested-by trailers for v1 yet.
Cover letter [U-Boot] [PATCH 0/4] USB and cache related fixes
Dear Tom Rini,
Quoted 5 lines
Hey all,
In commit b8adb12 the cache flushing behavior was changed for the EHCI stack. This change showed a few different problems on TI platforms (where our cacheline size is 64 not 32).
Good thing, it made a bug surface ;-)
Quoted 3 lines
First, the
dcache_offcall that
ehci-omap had been doing was now not happening soon enough to paper over the cache issues.
Hm, is the dcache_off() call implemented properly so nothing is lost when you shut off the cache btw?
Quoted 11 lines
This call is removed in patch 1. Second, when we have
dcache support compiled in but turned off via 'dcache off' the cache routines spam the console about alignment issues when a cache flush is attempted. This is a problem in that it makes operations extremely slow (as we're spending all our time spitting messages to console). The second patch makes the flush routines return when the dcache is off. The last two patches deal with the same problem, for EHCI and for MUSB. The USB spec says that 32 bytes is the minimum alignment but we need larger alignment when the cache is larger. Note that we can't useMAX()here as gcc doesn't allow that expansion inside of align(..).
Quoted 2 lines
Tested on
omap3_beagle(which was previously broken) and a MAKEALL -a arm looks good too.
Good job Tom, thanks for spending time on fixing this!
Best regards,
Marek Vasut