x86: rework tlb range flushing code
Get series with b4
b4 am [email protected]Versions newest first
- v1 Latest7 patches 0 repliesNew
Changes from v2 from the cover letter
* Added a brief comment above the ceiling tunable
* Updated the documentation to mention large pages and say "individual flush" instead of invlpg in most cases.
Patches in v1 No applies recorded yet
| # | Subject and files | Size | Replies | Applied |
|---|---|---|---|---|
| 1/7 | x86: mm: clean up tlb flushing codearch/ | +11 | 0 replies | |
| 2/7 | x86: mm: rip out complicated, out-of-date, buggy TLB flushingarch/ arch/ arch/ +2 more | +11 | 0 replies | |
| 3/7 | x86: mm: fix missed global TLB flush statarch/ | +7 | 0 replies | |
| 4/7 | x86: mm: trace tlb flushesarch/ arch/ include/ +3 more | +76 | 0 replies | |
| 5/7 | x86: mm: new tunable for single vs full TLB flushDocumentation/ arch/ | +118 | 0 replies | |
| 6/7 | x86: mm: set TLB flush tunable to sane valuearch/ | +1 | 0 replies | |
| 7/7 | big time hack: instrument flush timesarch/ | +112 | 0 replies |
Reviews trailers per patch
No Reviewed-by, Acked-by or Tested-by trailers for v1 yet.
Cover letter [PATCH 0/7] x86: rework tlb range flushing code
Changes from v2:
* Added a brief comment above the ceiling tunable
* Updated the documentation to mention large pages and say "individual flush" instead of invlpg in most cases.
Reposting with an instrumentation patch, and a few minor tweaks. I'd love some more eyeballs on this, but I think it's ready for -mm.
I'm having it run through the LKP harness to see if any perfmance regressions (or gains) show up.
Without the last (instrumentation/debugging) patch:
arch/x86/include/asm/mmu_context.h | 6 ++ arch/x86/include/asm/processor.h | 1 arch/x86/kernel/cpu/amd.c | 7 -- arch/x86/kernel/cpu/common.c | 13 ----- arch/x86/kernel/cpu/intel.c | 26 ---------- arch/x86/mm/tlb.c | 91 +++++++++++++++---------------------- include/linux/mm_types.h | 10 ++++ mm/Makefile | 2 8 files changed, 58 insertions(+), 98 deletions(-)
--
I originally went to look at this becuase I realized that newer CPUs were not present in the intel_tlb_flushall_shift_set() code.
I went to try to figure out where to stick newer CPUs (do we consider them more like SandyBridge or IvyBridge), and was not able to repeat the original experiments.
Instead, this set does:
1. Rework the code a bit to ready it for tracepoints
2. Add tracepoints
3. Add a new tunable and set it to a sane value