ARM SMMU fixes
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Cover letter [PATCH 0/2] ARM SMMU fixes
Quoted 1 line · Laurent Pinchart
Hi Will,
Hi Laurent,
Quoted 7 lines
On a different but related topic, I've written an
ipmmu-vmsa.cdriver for a Renesas IOMMU. The IP core has custom registers but uses VMSA-compatible page tables. What would you think about sharing the page table management code between the two drivers ? The biggest difference between the two implementations is that I've hardcoded the long descriptor format, while you have reused more system MMU macros that make the arm-smmu driver use 2 or 3 levels of page tables depending on whether LPAE is disabled or enabled.
Actually, my driver also only supports the long-descriptor format, so the code should be shareable. Things I support that you might have issues with are:
- Stage-1 and Stage-2 formats (although long-descriptor only)
- 4k and 64k pages (the latter for arm64 only)
- Contiguous pte hints
Do you have support for section mappings in your driver? That is something I'd be keen to add for the ARM SMMU, but it really complicates the code.
Will